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Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
Preliminary Technical Data
FEATURES
Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 62053-23 Compatible with 3-phase, 3 or 4 wire (delta or wye) and other 3-phase services Supplies total (fundamental and harmonic) active/reactive/ apparent energy on each phase and on the overall system Less than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at 25C Less than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at 25C Supports current transformer and di/dt current sensors Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at 25C Supplies sampled waveform data on all 3 phases Selectable No-load threshold level for total active, reactive and apparent powers Phase angle measurements in both current and voltage channels with max 0.3 error Wide supply voltage operation 2.4 to 3.7V Reference 1.2 V (drift 10 ppm/C typ) with external overdrive capability Single 3.3 V supply 40-Lead Frame Chip Scale (LFCSP) Lead Free Package Operating temperature -40 to 85C Flexible I2C, SPI(R), HSDC serial interfaces
ADE7858
processing required to perform total (fundamental and harmonic) active, reactive and apparent energy measurement, and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The ADE7858 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, with both three and four wires. The ADE7858 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2 and CF3 logic outputs provide a wide choice of power information: total active/reactive/apparent power or sum of current rms values. The ADE7858 has waveform sample registers that allow access to all ADC outputs. The device also incorporates power quality measurements such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement and angles between phase voltages and currents. Two serial interfaces can be used to communicate with the ADE7858: SPI or I2C while a dedicated high speed interface, HSDC (High Speed Data Capture) port, can be used in conjunction with I2C to provide access to the ADC outputs and real time power information. The ADE7858 has also two interrupt request pins, IRQ0 and IRQ1 , to indicate that an enabled interrupt event has occurred. The ADE7858 is available in 40-lead LFCSP lead free package.
GENERAL DESCRIPTION
The ADE78581 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7858 incorporates second-order - ADCs, a digital integrator, reference circuitry, and all the signal
1
U.S. patents pending.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADE7858 TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings.......................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 14 Test Circuit ...................................................................................... 15 Power Management ........................................................................ 16 PSM0 - Normal Power Mode ............................................... 16 PSM3 - Sleep Mode ............................................................... 16 Power Up Procedure .............................................................. 16 Hardware Reset ....................................................................... 17 Software Reset Functionality ................................................ 17 Theory of Operation ...................................................................... 19 Analog Inputs .............................................................................. 19 Analog to Digital Conversion ................................................... 19 Antialiasing Filter ................................................................... 20 ADC Transfer Function ......................................................... 20 Current Channel ADC............................................................... 20 Current Waveform Gain Registers ....................................... 20 Current Channel HPF ........................................................... 21 Current Channel Sampling ................................................... 21 di/dt Curent Sensor And Digital Integrator ............................ 22 Voltage Channel ADC ............................................................... 22 Voltage Waveform Gain Registers ........................................ 23 Voltage Channel HPF ............................................................ 23 Voltage Channel Sampling .................................................... 23 Changing Phase Voltage Data Path .......................................... 23 Power Quality Measurements ................................................... 24 Zero Crossing Detection ....................................................... 24 Zero-Crossing Timeout ......................................................... 25 Phase Sequence Detection .................................................... 25 Time Interval Between Phases.............................................. 25 Period Measurement .............................................................. 26 Phase Voltage Sag Detection ................................................. 26 Peak Detection ........................................................................ 27
Rev. PrA| Page 2 of 76
Preliminary Technical Data
Overvoltage and Overcurrent Detection ............................ 28 Phase Compensation ................................................................. 29 Reference Circuit ........................................................................ 30 Digital Signal Processor............................................................. 30 Root Mean Square Measurement ............................................. 31 Current RMS Calculation ..................................................... 31 Voltage Channel RMS Calculation ...................................... 32 Voltage RMS Offset Compensation ..................................... 32 Active Power Calculation .......................................................... 33 Total Active Power Calculation ............................................ 33 Active Power Gain Calibration............................................. 34 Active Power Offset Calibration .......................................... 34 Sign of Active Power Calculation......................................... 34 Active Energy Calculation .................................................... 35 Integration Time Under Steady Load .................................. 36 Energy Accumulation Modes ............................................... 36 Line Cycle Active Energy Accumulation Mode ................. 36 Reactive Power Calculation ...................................................... 37 Reactive Power Gain Calibration ......................................... 38 Reactive Power Offset Calibration ....................................... 38 Sign of Reactive Power Calculation ..................................... 38 Reactive Energy Calculation................................................. 39 Integration Time Under Steady Load .................................. 40 Energy Accumulation Modes ............................................... 40 Line Cycle Reactive Energy Accumulation Mode ............. 40 Apparent Power Calculation ..................................................... 41 Apparent Power Gain Calibration ....................................... 41 Apparent Power Offset Calibration ..................................... 42 Apparent Power Calculation using VNOM........................ 42 Apparent Energy Calculation ............................................... 42 Integration Time Under Steady Load .................................. 43 Energy Accumulation Mode................................................. 43 Line Cycle Apparent Energy Accumulation Mode............ 43 Waveform Sampling Mode ....................................................... 43 Energy to Frequency Conversion............................................. 44 Synchronizing energy registers with CFx outputs ............ 45 CF outputs for various accumulation modes ..................... 46 Sign of sum of phase powers in CFx data path .................. 47 No-Load Condition ................................................................... 47
Preliminary Technical Data
No-load detection based on total active and reactive powers.......................................................................................47 No-load detection based on apparent power ......................48 Checksum Register .....................................................................48 Interrupts......................................................................................49 Using the Interrupts with an MCU ......................................50 Serial Interfaces ...........................................................................50 Serial interface choice .............................................................50
ADE7858
I2C Compatible Interface ....................................................... 51 SPI Compatible Interface ....................................................... 52 HSDC Interface ....................................................................... 54 Registers List .................................................................................... 57 Outline Dimensions ........................................................................ 73 Ordering Guide ........................................................................... 73
Rev. PrA | Page 3 of 76
ADE7858 FUNCTIONAL BLOCK DIAGRAM
RESET
Preliminary Technical Data
REFin/out 17 VDD 26 AGND 25 AVDD 24 DVDD 5 DGND 6 AIRMSOS LPF
4
CLKIN CLKOUT
27 POR 28 1.2V REF LDO LDO
x2
LPF
AIRMS
AVAGAIN
2 3
PM0 PM1
x2
AIGAIN IAP IAN 7 8 PGA1 ADC
HPFDIS[23:0]
AVRMS CF1DEN
Digital Integrator AVRMSOS AWATTOS LPF AWGAIN DFC
APHCAL AVGAIN
HPF
:
CF2DEN
33
CF1
HPFDIS[23:0]
VAP
23
PGA3 ADC
HPF Phase A,B and C data AVAROS AVARGAIN CF3DEN DFC
:
34
CF2
IBP IBN VBP
9 12 22
PGA1 ADC TOTAL ACTIVE/ REACTIVE/ APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE B (see phase A for detailed data path)
Computational Block for Total Reactive Power
DFC
:
35
CF3/HSCLK
PGA3 ADC
29 ICP ICN VCP VN 13 14 19 18 PGA3 ADC PGA1 ADC TOTAL ACTIVE/ REACTIVE/ APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE C (see phase A for detailed data path) SPI/I2C 32 36 38
IRQ0 IRQ1 SCLK/SCL MOSI/SDA MISO/HSD
Digital Signal Processor
I2C
37 39
SS /HSA
HSDC
Figure 1. ADE7858 Functional Block Diagram
Rev. PrA| Page 4 of 76
Preliminary Technical Data SPECIFICATIONS
VDD = 3.3 V 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = -40C to +85C. Table 1.
Parameter1, 2 ACCURACY ACTIVE ENERGY MEASUREMENT Total Active Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Total Active Energy Measurement Bandwidth REACTIVE ENERGY MEASUREMENT Total Reactive Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Total Reactive Energy Measurement Bandwidth RMS MEASUREMENTS IRMS and VRMS Measurement Bandwidth IRMS and VRMS Measurement Error (PSM0 mode3) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) ADC Offset Error Gain Error WAVEFORM SAMPLING Current and Voltage Channels Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Bandwidth (-3 dB) Specification Unit Test Conditions/Comments
ADE7858
0.1 0.2 0.1 0.05 0.05
% typ % typ %typ max max
Over a dynamic range of 1000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 3000 to 1, PGA=1,2,4; integrator off Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37 Phase lag 60 TBD Conditions
0.01 0.01 2
% typ TBD Conditions % typ kHz typ
0.1 0.2 0.1 0.05 0.05
% typ % typ %typ max max
Over a dynamic range of 1000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 3000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37 Phase lag 60 TBD Conditions
0.01 0.01 2
% typ TBD Conditions % typ kHz typ
2 0.1
kHz typ % typ Over a dynamic range of 1000:1, PGA=1
500 400 25 4
mV peak, Max k min mV max % typ
Differential inputs: IAP-IAN, IBP-IBN, ICP-ICN Single ended inputs: VAP-VN, VBP-VN, VCP-VN Uncalibrated error, see the Terminology section External 1.2 V reference Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS See Waveform Sampling Mode chapter
55 62 2
dB typ dB typ kHz
Rev. PrA | Page 5 of 76
ADE7858
Parameter1, 2 TIME INTERVAL BETWEEN PHASES Measurement error CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency Duty Cycle Active Low Pulse Width Jitter REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE (PSM0 mode3) Reference Error Output Impedance Temperature Coefficient Specification 0.3 8 50 80 0.04 1.3 1.1 10 0.9 4 10 50 CLKIN Input Clock Frequency Crystal equivalent series resistance CLKIN input capacitance CLKOUT output capacitance LOGIC INPUTS--MOSI/SDA, SCLK/SCL, CLKIN and SS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS-- IRQ0 , IRQ1 , MISO/HSDATA, HSCLK and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL CF1, CF2, CF3 Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY in PSM0 mode VDD IDD POWER SUPPLY in PSM3 mode3 VDD IDD in PSM3 mode3
1 2
Preliminary Technical Data
Unit deg typ KHz % Msec % typ V max V min pF max mV max k min ppm/C typ ppm/C max All specifications CLKIN of 16.384 MHz 16.384 30 50 12 12 MHz max K min K max pF typ pF typ Test Conditions/Comments Line frequency = 45 Hz to 65 Hz, HPF on
If CF1, CF2 or CF3 frequency >6.25Hz If CF1, CF2 or CF3 frequency <6.25Hz For CF1, CF2 or CF3 frequency of 1Hz 1.2 V + 8% 1.2 V - 8% Nominal 1.2 V at REFIN/OUT pin
2.4 0.8 3 10
V min V max A max pF max
VDD = 3.3 V 10% VDD = 3.3 V 10% Typical 10 nA, VIN = 0 V to VDD DVDD = 3.3 V 10%
3.0 0.4 2.4 0.4 3.0 3.6 TBD 2.4 3.7 1
V min V max V min V max V min V max mA typ. V min V max A typ.
ISOURCE = 800 A ISINK = 2 mA ISOURCE = 500 A ISINK = 2 mA For specified performance 3.3 V - 10% 3.3 V + 10% For specified performance
See the Typical Performance Characteristics. See the Terminology section for a definition of the parameters. 3 See Power Management chapter for details on various power modes of the ADE7858
Rev. PrA| Page 6 of 76
Preliminary Technical Data
TIMING CHARACTERISTICS
VDD = 3.3 V 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz , TMIN to TMAX = -40C to +85C.
Table 2. I2C Compatible Interface Timing Parameter
Parameter SCL clock frequency Hold time (repeated) START condition. LOW period of SCL clock HIGH period of SCL clock Set-up time for a repeated START condition Data hold time Data setup time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of suppressed spikes Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF tSP Standard mode Min Max 0 100 4.0 4.7 4.0 4.7 0 3.45 250 1000 300 4.0 4.7 na
ADE7858
Fast Mode Min Max 0 400 0.6 1.3 0.6 0.6 0 0.9 100 20 300 20 300 0.6 1.3 50
Unit kHz s s s s s ns ns ns s s ns
SDA
tf tLOW tr
tSU;DAT tf
tHD;STA
tSP
tr
tBUF
SCLK tHD;STA tHD;DAT tHIGH tSU;STA tSU;STO
START CONDITION
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 2. I2C Compatible Interface Timing
Rev. PrA | Page 7 of 76
ADE7858
Table 3. SPI INTERFACE TIMING Parameter
Parameter Symbol tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDIS tSFS
Preliminary Technical Data
Min 50 400 175 175 5 20 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
SS to SCLK edge SCLK period SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time
MISO disable after SS rising edge
40
5 0
20 20 20 20 40
SS high after SCLK edge
SS
tSS
tSFS
SCLK tSL tDAV tSH tSF tSR tDIS
MISO
MSB
INTERMEDIATE BITS
LSB
tDF INTERMEDIATE BITS MOSI tDSU MSB IN tDHD
tDR
LSB IN
Figure 3. SPI Interface Timing
Rev. PrA| Page 8 of 76
Preliminary Technical Data
Table 4. HSDC INTERFACE TIMING Parameter
Parameter HSA to SCLK edge HSCLK period HSCLK low pulse width HSCLK high pulse width Data output valid after HSCLK edge Data output fall time Data output rise time HSCLK rise time HSCLK fall time HSD disable after HAS rising edge HSA high after HSCLK edge
HSA
ADE7858
Symbol tSS tSL tSH tDAV tDF tDR tSR tSF tDIS tSFS Min 0 125 50 50 5 Max Unit ns ns ns ns ns ns ns ns ns ns
40 20 20 10 10
40 0
tSS
tSFS
HSCLK tSL tDAV tSH tSF tSR tDIS
HSD
MSB
INTERMEDIATE BITS
LSB
tDF
tDR
Figure 4. HSDC Interface Timing
200A IOL
TO OUTPUT PIN
2.1V CL 50pF
04443-002
1.6mA
IOH
Figure 5. Load Circuit for Timing Specifications
Rev. PrA | Page 9 of 76
ADE7858 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted.
Table 5. Absolute Maximum Ratings
Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Industrial Range Storage Temperature Range 40-Lead LQFP, Power Dissipation JA Thermal Impedance JC Thermal Impedance Rating -0.3 V to +3.7 V -0.3 V to +3.7 V -2 V to +2 V
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
-0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C TBD mW 29.3C/W 1.8C/W
Rev. PrA| Page 10 of 76
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 40
ADE7858
SS /
HSA 39
MOSI/ MISO/ SCLK/ CF3/ CF2 SDA HSD SCL HSCLK 38 37 36 35 34
CF1 33
IRQ 1
32
NC 31
NC PM0 PM1
1 2 3 4 5 6 7 8 9 10
30 29 28 27
NC
IRQ0
CLKOUT CLKIN VDD AGND AVDD VAP VBP NC
RESET
DVDD DGND IAP IAN IBP NC
ADE7858 TOP VIEW (not to scale)
26 25 24 23 22 21
11 NC
12 IBN
13 ICP
14 ICN
15 NC
16 NC
17
18
19 VCP
20 NC
REFin/out VN
Figure 6. ADE7858 Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1,10,11,20,21,30,31,40 2 3 4 5 Mnemonic NC PM0 PM1
RESET
Description These pins are not connected internally. Power Mode pin 0. For proper operation, this pin should be set to VDD vis a 10k pull-up resistor. Power Mode pin 1. This pin defines the power mode of the ADE7858 as described in Table 7. Reset Input, active low. In PSM0, this pin should stay low for at least 10sec to trigger a hardware reset This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 4.7 F capacitor in parallel with a ceramic 220 nF capacitor. This provides the ground reference for the digital circuitry in the ADE7858. Analog Inputs for Current Channel. This channel is used with the current transducers and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with a maximum differential level of 0.5 V. This channel has also an internal PGA, for IAx, IBx and ICx. Connect to AGND. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V 0.075% and a maximum temperature coefficient of 50 ppm/C. An external reference source with 1.2V 8% can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 4.7 F capacitor in parallel with a ceramic 100nF capacitor. After reset, the on-chip reference is enabled. Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as the voltage channel in this document. These inputs are single-ended voltage inputs with the maximum signal level of 0.5 V with respect to VN for specified operation. This channel has also an internal PGA. This pin provides access to the on-chip 2.5V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 4.7 F capacitor in parallel with a ceramic 220 nF capacitor.
Rev. PrA | Page 11 of 76
DVDD
6 7,8, 9,12, 13,14, 15,16 17
DGND IAP, IAN, IBP, IBN, ICP, ICN, NC REFIN/OUT
18, 19, 22, 23
VN, VCP, VBP, VAP
24
AVDD
ADE7858
25 AGND
Preliminary Technical Data
This pin provides the ground reference for the analog circuitry in the ADE7858. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. This pin provides the supply voltage for the ADE7858. In PSM0 (normal power mode) the supply voltage should be maintained at 3.3 V 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low power mode) and PSM3 (sleep mode), when the ADE7858 is supplied from a battery, the supply voltage should be maintained between 2.4 and 3.7V. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. Master Clock for ADE7858. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7858. The clock frequency for specified operation is 16.384 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer's data sheet for the load capacitance requirements. A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7858. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a detailed presentation of the events that may trigger interrupts. Calibration Frequency (CF) Logic Outputs. Provide power information based on CF1SEL, CF2SEL, CF3SEL bits in CFMODE register. These outputs are used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the respectively CF1DEN, CF2DEN, CF3DEN registers (see the Energy to Frequency Conversion section).CF3 is multiplexed with the serial clock output of HSDC port. Serial Clock Input for SPI port / Serial Clock Input for I2C port. All serial data transfers are synchronized to this clock (see the Serial Interfaces section). This pin has a Schmidt-trigger input for use with a clock source that has a slow edge transition time, for example, optoisolator outputs. Data Out for SPI port / Data Out for HSDC port Data In for SPI port / Data Out for I2C port Slave Select for SPI port / HSDC port active The exposed pad should be connected to AGND.
26
VDD
27
CLKIN
28
CLKOUT
29, 32 33,34,35
IRQ0 , IRQ 1
CF1,CF2,CF3/HSCLK
36
SCLK/SCL
37 38 39 EPAD
MISO/HSD MOSI/SDA
SS /HSA Exposed Pad
Rev. PrA| Page 12 of 76
Preliminary Technical Data TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE7858 is defined by
Measurement Error Energy Registered by ADE7858 - True Energy 100% True Energy
ADE7858
selection (see the Typical Performance Characteristics section). However, the offset is removed from the current and voltage channels by a HPF and the power calculation is not affected by this offset.
Gain Error The gain error in the ADCs of the ADE7858 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code. Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2, 4, 8 or 16. It is expressed as a percentage of the output ADC code obtained under a gain of 1. CF Jitter
(1)
Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all-digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. Power Supply Rejection (PSR) This quantifies the ADE7858 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (TBD mV rms/TBD Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading--see the Measurement Error definition.
The period of pulses at one of CF1, CF2 or CF3 pins is continuously measured. The maximum, minimum and average values of 4 consecutive pulses are computed: MAX max( Period 0 , Period1 , Period 2 , Period 3 ) MIN min( Period 0 , Period1 , Period 2 , Period 3 )
AVG Period 0 Period1 Period 2 Period 3 4 MAX MIN 100[%] AVG
For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied 10%. Any error introduced is again expressed as a percentage of the reading.
ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND that the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range
The CF jitter is then computed as
CF jitter
(2)
Rev. PrA | Page 13 of 76
ADE7858 TYPICAL PERFORMANCE CHARACTERISTICS
TBD
Preliminary Technical Data
Rev. PrA| Page 14 of 76
Preliminary Technical Data TEST CIRCUIT
4.7uF 0.22uF 10uF 0.1uF
ADE7858
24
26
5
AVDD
3.3V
2 3 4
DVDD
PM0 PM1 RESET
VDD
SS_N_HSA MOSI_SDA MISO_HSD
39 38 37 36 35
10K 3.3V
10K
1uF
1K
1.8nF 1.8nF
7 8 9 12 13 14 18 19
IAP SCLK_SCL IAN CF3_HSCLK IBP CF2 IBN ICP IRQ1_N ICN IRQ0_N VN REFIN_OUT VCP CLKOUT DGND AGND
28
16.384MHz
1K
Same as IAP, IAN Same as IAP, IAN
1K 1.8nF
34 33 32 29 17
20pF 4.7uF 0.1uF
ADE7858
CF1
Same as CF2 Same as IRQ0_N
3.3V
1.5K
10K
1K
1.8nF
Same as VCP Same as VCP
22 23
VBP VAP
PAD
CLKIN
27
20pF
6
25
Figure 7. Test Circuit
Rev. PrA | Page 15 of 76
ADE7858 POWER MANAGEMENT
The ADE7858 has two modes of operation, determined by the state of PM0 and PM1 pins (see Table 7). These pins provide a complete control of ADE7858 operation and could easily be connected to an external microprocessor I/O. The PM1 pin has an internal pull up resistor. Table 8 lists actions that are recommended before and after setting a new power mode. Table 9 presents actions that are recommended before and after setting a new power mode.
Table 7. ADE7858 Power Supply Modes
Power Supply Modes PSM0 - normal power mode PSM3 - sleep mode PM1 0 1
Preliminary Technical Data
high by writing STATUS1[31:0] register with the corresponding bit set to 1. The bit 15 (RSTDONE) in interrupt mask register does not have any functionality attached even if IRQ1 pin goes low when bit 15 (RSTDONE) in STATUS1[31:0] is set to 1. This makes RSTDONE interrupt unmaskable.
PSM3 - Sleep Mode
In this mode, ADE7858 has most of the internal circuits of the ADE7854 are turned off and the current consumption is the lowest. The I2C, HSDC or SPI ports are not functional during this mode. The pins RESET , SCLK/SCL, MOSI/SDA and SS /HSA should be set high.
Power Up Procedure
The ADE7858 contains an on-chip power supply monitor that supervises the power supply VDD. At power up, until VDD reaches 2V 10%, the chip is in an inactive state. As VDD crosses this threshold, the power supply monitor keeps the chip in this inactive state for 26msec more, allowing VDD to achieve 3.3V-10%, the minimum recommended supply voltage. As PM1 pin has an internal pull up resistors and the external microprocessor keeps it high, the ADE7858 always powers up in sleep mode PSM3. Then, an external circuit (i.e. microprocessor) sets PM1 pin to low level, allowing the ADE7858 to enter normal mode PSM0. The passage from PSM3 mode in which most of the internal circuitry is turned off to PSM0 mode in which all functionality is enabled is done in less than 40msec. See Figure 8 for details.
PSM0 - Normal Power Mode
In PSM0 mode, the ADE7858 is fully functional. The PM1 pin is set to low for the ADE7858 to enter this mode. If the ADE7858 is in PSM3 mode and is switched into PSM0 mode, all control registers take the default values with the exception of CONFIG2[7:0] register that maintains its value. The ADE7858 signals the end of the transition period by triggering IRQ1 interrupt pin low and setting bit 15 (RSTDONE) in STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition is finished. The status bit is cleared and IRQ1 pin is set back
3.3V-10%
2.0V+/-10%
ADE7858 PSM0 ready
0V
26msec
40msec
ADE7858 Powered UP
POR timer turned ON
ADE7858 enters PSM3
Microprocessor sets ADE7858 in PSM0
Microprocessor makes the choice between RSTDONE I2C and SPI interrupt triggered
Figure 8. ADE7858 power up procedure
As the ADE7858 enters PSM0 mode, the I2C port is the active serial port. If the SPI port is used, then the SS pin must be
toggled three times high to low. This action selects the ADE7858 into using the SPI port for further use. If I2C is the
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Preliminary Technical Data
active serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to 1 to lock it in. From this moment on, the ADE7858 ignores spurious togglings of the SS pin and an eventual switch into using SPI port is no longer possible. If SPI is the active serial port, any write to CONFIG2[7:0] registers locks the port. From this moment on, a switch into using I2C port is no longer possible. Only a power down or setting RESET pin low resets back the ADE7858 to use the I2C port. Once locked, the serial port choice is maintained when the ADE7858 changes PSMx, x=0, 1, 2, 3 power modes. Immediately after entering PSM0, the ADE7858 sets all registers to their default values, including CONFIG2[7:0]. The ADE7858 signals the end of the transition period by triggering IRQ1 interrupt pin low and setting bit 15 (RSTDONE) in STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and IRQ1 pin is set back high by writing STATUS1[31:0] register with the corresponding bit set to 1. As the RSTDONE is an unmaskable interrupt, bit 15 (RSTDONE) in STATUS1[31:0] register has to be cancelled in order for the IRQ1 pin to turn back high. It is recommended to wait until IRQ1 pin goes low before accessing STATUS1[31:0] register to test the state of RSTDONE bit. At this point, as a good programming practice, it is also recommended to cancel all other status flags in STATUS1[31:0] and STATUS0[31:0] registers by writing the corresponding bits with 1. Initially, the DSP is in idle mode, which means it does not execute any instruction. This is the moment to initialize all ADE7858 registers and then write 0x0001 into the RUN[15:0] register to start the DSP (see Digital Signal Processor chapter for details on the RUN[15:0] register). If the supply voltage VDD becomes lower than 2V 10%, the ADE7858 goes into inactive state, which means no measurements and computations are executed.
ADE7858
registers are set to their default values, including CONFIG2[7:0]. The ADE7858 signals the end of the transition period by triggering IRQ1 interrupt pin low and setting bit 15 (RSTDONE) in STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and IRQ1 pin is set back high by writing STATUS1[31:0] register with the corresponding bit set to 1. After a hardware reset, the DSP is in idle mode, which means it does not execute any instruction. As the I2C port is the default serial port of the ADE7858, it becomes active after a reset state. If SPI is the port used by the external microprocessor, the procedure to enable it has to be repeated immediately after RESET pin is toggled back high. See Serial Interfaces chapter for details. At this point, it is recommended to initialize all ADE7858 registers and then write 0x0001 into the RUN[15:0] register to start the DSP (see Digital Signal Processor chapter for details on RUN[15:0] register).
Software Reset Functionality
Bit 7 (SWRST) in CONFIG[15:0] register manages the software reset functionality in PSM0 mode. The default value of this bit is 0. If this bit is set to 1, then the ADE7858 enters a software reset state. In this state, almost all internal registers are set to their default value. In addition, the choice of what serial port I2C or SPI is in use remains unchanged if the lock in procedure has been previously executed (See Serial Interfaces chapter for details). The register that maintains its value despite SWRST bit being set to 1 is CONFIG2[7:0]. When the software reset ends, bit 7 (SWRST) in CONFIG[15:0] is cleared to 0, the IRQ1 interrupt pin is set low and bit 15 (RSTDONE) in STATUS1[31:0] register is set to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and IRQ1 pin is set back high by writing STATUS1[31:0] register with the corresponding bit set to 1. After a software reset ended, the DSP is in idle mode, which means it does not execute any instruction. It is recommended to initialize all the ADE7858 registers and then write 0x0001 into the RUN[15:0] register to start the DSP (see Digital Signal Processor chapter for details on the RUN[15:0] register). Software reset functionality is not available in PSM3 mode.
Hardware Reset
The ADE7858 has a RESET pin. If the ADE7858 is in PSM0 mode and RESET pin is set low, then the ADE7858 enters in hardware reset state. The ADE7858 has to be in PSM0 mode for hardware reset to be considered. Setting RESET pin low while the ADE7858 is in PSM1, PSM2 and PSM3 modes does not have any effect. If the ADE7858 is in PSM0 mode and RESET pin is toggled from high to low and then back high after at least 10sec, all the
Table 8: ADE7858 Power modes and related characteristics
Power Mode PSM0 Registers Set to default Set to default CONFIG2 Set to default Unchanged
State after hardware reset State after software reset
I2C/SPI I2C enabled Active serial port unchanged if lock in procedure has been previously
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Functionality -All circuits are active. DSP is in idle mode. -All circuits are active. DSP is in idle mode.
ADE7858
Power Mode PSM3 Registers Not available CONFIG2 Values set during PSM0 unchanged I2C/SPI executed Disabled
Preliminary Technical Data
Functionality -Internal circuits shut down. -Serial ports not available.
Table 9. Recommended actions when changing power modes
Initial Power Mode PSM0 Recommended actions before setting next power mode -Stop DSP by setting RUN[15:0]=0x0000. -Disable HSDC by clearing bit 6 (HSDEN) to 0 in CONFIG[15:0] register. -Mask interrupts by setting MASK0[31:0]=0x0 and MASK1[31:0]=0x0 . -Erase interrupt status flags in STATUS0[31:0] and STATUS1[31:0] registers. -No action necessary PSM0 PSM3 -No action necessary
PSM3
-Wait until IRQ1 pin triggered low -Poll STATUS1[31:0] register until bit 15 (RSTDONE) set to 1
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Preliminary Technical Data THEORY OF OPERATION
ANALOG INPUTS
The ADE7858 has six analog inputs forming current and voltage channels. The current channels consist of four pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN and ICP and ICN. These voltage input pairs have a maximum differential signal of 0.5 V. In addition, the maximum signal level on analog inputs for IxP/IxN is 0.5 V with respect to AGND. The maximum common mode signal allowed on the inputs is 25 mV. Figure 9 presents a schematic of the current channels inputs and their relation to the maximum common mode voltage. All inputs have a programmable gain amplifier (PGA) with possible gain selection of 1, 2, 4, 8 or 16. The gain of IA, IB and IC inputs is set in bits 2-0 (PGA1) of GAIN[15:0] register. See Table 35 for details on GAIN[15:0] register. The voltage channel has three single-ended voltage inputs: VAP, VBP and VCP. These single-ended voltage inputs have a maximum input voltage of 0.5 V with respect to VN. In addition, the maximum signal level on analog inputs for VxP and VN is 0.5 V with respect to AGND. The maximum common mode signal allowed on the inputs is 25 mV. Figure 11 presents a schematic of the voltage channels inputs and their relation to the maximum common mode voltage. All inputs have a programmable gain with possible gain selection of 1, 2, 4, 8, or 16. The setting is done using bits 8-6 (PGA3) in GAIN[15:0] register - see Table 35. Figure 10 shows how the gain selection from GAIN[15:0] register works in both current and voltage channels.
DIFFERENTIAL INPUT V1+V2=500mV MAX PEAK V1+V2 +500mV COMMON MODE VCM=+/-25mV MAX + IAP, IBP or ICP +
ANALOG LOW-PASS FILTER
ADE7858
clock. In the ADE7858, the sampling clock is equal to 1.024MHz (CLKIN/16). The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and therefore the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.
IxP, VxP
GAIN SELECTION
VIN
K x VIN
IxN, VN x=A,B,C
Figure 10. PGA in current and voltage channels
DIFFERENTIAL INPUT V1+V2=500mV MAX PEAK V1 +500mV COMMON MODE VCM=+/-25mV MAX + VAP, VBP or VCP
V1
+ -
VCM + VN VCM
-500mV
V1
Figure 11. Maximum input level, voltage channels, Gain=1
CLKIN/16 INTEGRATOR + C - VREF
+ -
VCM + -500mV VCM + V2 IAN, IBN or ICN
R
LATCHED COMPARATOR
DIGITAL LOW-PASS FILTER 24
Figure 9. Maximum input level, current channels, Gain=1
.....10100101..... 1-BIT DAC
ANALOG TO DIGITAL CONVERSION
The ADE7858 has six sigma-delta Analog to Digital Converters (ADC). In PSM0 mode, all ADCs are active. In PSM3 mode, the ADCs are powered down to minimize power consumption. For simplicity, the block diagram in Figure 12 shows a firstorder - ADC. The converter is made up of the - modulator and the digital low-pass filter. A - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling
Figure 12. First-Order - ADC
The - converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7858 is 1.024MHz and the bandwidth of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the
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ADE7858
quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered -- see Figure 13. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the - modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. This is the second technique used to achieve high resolution. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 13.
Digital Filter SIGNAL Antialias Filter (RC) Shaped Noise Sampling Frequency NOISE
Preliminary Technical Data
attenuation to be sufficiently high at the sampling frequency of 1.024MHz. The 20 dB per decade attenuation of this filter is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes 20 dB per decade attenuation produced by the LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade one more RC filter, so a -40 dB per decade attenuation is produced.
ALIASING EFFECTS Sampling Frequency
0
2
4
512 Frequency [KHz]
1024
IMAGE FREQUENCIES
Figure 14. Aliasing effects at ADE7858
0 24 512 Frequency [KHz] 1024
ADC Transfer Function
All ADCs in the ADE7858 are designed to produce the same 24-bit signed output code for the same input signal level. With a full-scale input signal of 0.5 V and an internal reference of 1.2 V, the ADC output code is nominally 5,928,256 (0x5A7540). The code from the ADC may vary between 0x800000 (-8,388,608) and 0x7FFFFF (+8,388,607); this is equivalent to an input signal level of 0.707V. However, for specified performance, it is recommended not to exceed the nominal range of 0.5V. The ADC performance is guaranteed only for input signals lower than 0.5V.
SIGNAL
High Resolution Output From Digital LPF
NOISE
0
2
4
512 Frequency [KHz]
1024
Figure 13. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
CURRENT CHANNEL ADC
Figure 17 shows the ADC and signal processing path for the input IA of the current channels (same for IB and IC). The ADC outputs are signed twos complement 24-bit data-words and are available at a rate of 8 kSPS (thousand samples per second). With the specified full-scale analog input signal of 0.5V, the ADC produces its maximum output code value. This diagram shows a full-scale voltage signal being applied to the differential inputs IAP and IAN. The ADC output swings between -5,928,256 (0xA58AC0 ) and+5,928,256 (0x5A7540).
Antialiasing Filter
Figure 12 also shows an analog low-pass filter (RC) on the input to the ADC. This filter is placed outside the ADE7858 and its role is to prevent aliasing. Aliasing is an artifact of all sampled systems and is illustrated in Figure 14. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency, i.e., 512 kHz) are imaged or folded back down below 512 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 1.024MHz, move into the band of interest for metering, i.e., 40 Hz to 2 kHz. To attenuate the high frequency (near 1.024MHz) noise and prevent the distortion of the band of interest, a LPF (low-pass filter) has to be introduced. For conventional current sensors, it is recommended to use one RC filter with a corner frequency of 5 KHz in order for the
Current Waveform Gain Registers
There is a multiplier in the signal path of each phase current. The current waveform can be changed by 100% by writing a correspondent twos complement number to the 24-bit signed current waveform gain registers (AIGAIN[23:0], BIGAIN[23:0] and CIGAIN[23:0]). For example, if 0x400000 is written to those registers, the ADC output is scaled up by 50%. To scale the input by -50%, write 0xC00000 to the registers. Equation (3) describes mathematically the function of the current waveform gain registers.
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Preliminary Technical Data
Current waveform Content of Current Gain Register ADC Output x 1 2 23
ADE7858
(3) currents and of the phase voltages. If enabled, the HPF eliminates any dc offset on the current channel. All filters are implemented in the DSP and by default they are all enabled: 24bit register HPFDIS[23:0] is cleared to 0x00000000. All filters are disabled by setting HPHDIS[23:0] to any non zero value. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. The HPFDIS register is accessed as a 32bit register with 8 most significant bits padded with 0s. See Figure 16 for details.
Changing the content of AIGAIN[23:0], BIGAIN[23:0] or CIGAIN[23:0] affects all calculations based on its current; that is, it affects the corresponding phase active/reactive/apparent energy and current rms calculation. In addition, waveform samples are also scaled accordingly. Note that the serial ports of the ADE7858 work on 32, 16 or 8bit words and the DSP works on 28 bits. The 24-bit AIGAIN, BIGAIN and CIGAIN registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits. See Figure 15 for details.
31
24
23 24 bit number
0
0000 0000
Current Channel Sampling
Figure 16. 24-bit HPFDIS register is transmitted as 32-bit word
31 28 27 0000
24 23 24 bit number
0
bits 27-24 equal bit 23 is sign bit to bit 23
Figure 15. 24-bit xIGAIN (x=A,B,C,N) are transmitted as 32-bit words
The waveform samples of the current channel are taken at the output of HPF and stored into IAWV, IBWV, ICWV 24-bit signed registers at a rate of 8kSPS. All power and rms calculations remain uninterrupted during this process. Bit 17 (DREADY) in STATUS0[31:0] register is set when IAWV, IBWV and ICWV registers are available to be read using I2C or SPI serial ports. Setting bit 17 (DREADY) in MASK0[31:0] register enables an interrupt to be set when the DREADY flag is set. See Digital Signal Processor chapter for more details on bit DREADY.
Current Channel HPF
The ADC outputs can contain a dc offset. This offset may create errors in power and rms calculations. High Pass Filters (HPF) are placed in the signal path of the phase and neutral
LPF1
ZX DETECTION ZX SIGNAL DATA RANGE 0x5A7540= 5,928,256
CURRENT PEAK, OVERCURRENT DETECT PGA1 bits GAIN[2:0] x1, x2, x4,x8, x16 IAP DSP REFERENCE AIGAIN[23:0] HPFDIS[23:0] HPF DIGITAL INTEGRATOR INTEN bit CONFIG[0]
0V
CURRENT RMS (IRMS) CALCULATION IAWV WAVEFORM SAMPLE REGISTER TOTAL ACTIVE POWER CALCULATION
0xA58AC0= -5,928,256
VIN IAN
PGA1
ADC
VIN +0.5V/GAIN 0x5A7540= 5,928,256
CURRENT CHANNEL DATA RANGE 0x5A7540= 5,928,256
CURRENT CHANNEL DATA RANGE AFTER INTEGRATOR
0V
0V
0V
-0.5V/GAIN ANALOG INPUT RANGE
0xA58AC0= -5,928,256 ADC OUTPUT RANGE
0xA58AC0= -5,928,256
Figure 17. Current Channel Signal Path
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ADE7858
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. When IAWV, IBWV, ICWV 24-bit signed registers are read from the ADE7858, they are transmitted signed extended to 32 bits. See Figure 18 for details.
Preliminary Technical Data
significant high frequency noise. An antialiasing filter of at least the second order is needed to avoid that the noise alias back in the band of interest when the ADC is sampling (see the Antialiasing Filter section).
31
24 23 22 0 24 bit signed number
bits 31-24 equal to bit 23
bit 23 is sign bit
Figure 18. 24-bit IxWV (x=A, B, C) are transmitted as 32-bit signed words
The ADE7858 contains a High Speed Data Capture (HSDC) port that is specially designed to provide fast access to the waveform sample registers. See HSDC Interface section for more details.
di/dt CURENT SENSOR AND DIGITAL INTEGRATOR
The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 19 shows the principle of a di/dt current sensor.
Figure 20. Combined Gain and Phase Response of the Digital Integrator
MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)
DICOEFF[23:0] 24-bit signed register is used in the digital integrator algorithm. At power up or after a reset, its value is 0x000000. Before turning on the integrator, this register must be initialized with 0xFF8000. DICOEFF[23:0] is not used when the integrator is turned off and can be left at 0x000000 in this case.
-15
MAGNITUDE (dB)
-20 -25 -30 30 -89.96
Figure 19. Principle of a di/dt Current Sensor
04443-042
+ EMF (ELECTROMOTIVE FORCE) - INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt)
35
40
The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. Due to the di/dt sensor, the current signal needs to be filtered before it can be used for power measurement. On each phase currents data paths, there is a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator is disabled by default when the ADE7858 is powered up and after reset. Setting bit 0 (INTEN) of the CONFIG[15:0] register turns on the integrator. Figure 20 and Figure 21 show the magnitude and phase response of the digital integrator. Note that the integrator has a -20 dB/dec attenuation and approximately -90 phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates
45 50 55 FREQUENCY (Hz)
60
65
70
PHASE (Degrees)
-89.97
-89.98 -89.99 30
35
40
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 21. Combined Gain and Phase Response of the Digital Integrator (40 Hz to 70 Hz)
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the registers presented in Figure 15, DICOEFF[23:0] 24-bit signed register is accessed as a 32-bit register with 4 most significant bits padded with 0s and sign extended to 28 bits. When the digital integrator is switched off, the ADE7858 can be used directly with a conventional current sensor, such as a current transformer (CT).
VOLTAGE CHANNEL ADC
Figure 22 shows the ADC and signal processing chain for the input VA in the voltage channel. The VB and VC channels have
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08017-101
Preliminary Technical Data
similar processing chains. The ADC outputs are signed twos complement 24-bit words and are available at a rate of 8 kSPS. With the specified full-scale analog input signal of 0.5 V, the ADC produces its maximum output code value. This diagram shows a full-scale voltage signal being applied to the differential inputs VA and VN. The ADC output swings between -5,928,256 (0xA558AC0) and +5,928,256 (0x5A7540).
ADE7858
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. As presented in Figure 15, AVGAIN, BVGAIN and CVGAIN registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
Voltage Channel HPF
As seen in Current Channel HPF section, the ADC outputs can contain a dc offset that can create errors in power and rms calculations. High Pass Filters (HPF) are placed in the signal path of the phase voltages, similar to the ones in the current channels. HPFDIS[23:0] register may enable or disable the filters. See Current Channel HPF section for more details.
Voltage Waveform Gain Registers
There is a multiplier in the signal path of each phase voltage. The voltage waveform can be changed by 100% by writing a correspondent twos complement number to the 24-bit signed current waveform gain registers (AVGAIN[23:0], BVGAIN[23:0] and CVGAIN[23:0]). For example, if 0x400000 is written to those registers, the ADC output is scaled up by 50%. To scale the input by -50%, write 0xC00000 to the registers. Equation (4) describes mathematically the function of the current waveform gain registers.
Voltage waveform Content of Voltage Gain Register ADC Output x 1 2 23
(4)
Voltage Channel Sampling
The waveform samples of the current channel are taken at the output of HPF and stored into VAWV, VBWV and VCWV 24bit signed registers at a rate of 8kSPS. All power and rms calculations remain uninterrupted during this process. Bit 17 (DREADY) in STATUS0[31:0] register is set when VAWV, VBWV and VCWV registers are available to be read using I2C or SPI serial ports. Setting bit 17 (DREADY) in MASK0[31:0] register enables an interrupt to be set when the DREADY flag is set. See Digital Signal Processor chapter for more details on bit DREADY.
Changing the content of AVGAIN[23:0], BVGAIN[23:0] and CVGAIN[23:0] affects all calculations based on its voltage; that is, it affects the corresponding phase active/reactive/apparent energy and voltage rms calculation. In addition, waveform samples are also scaled accordingly.
VOLTAGE PEAK, OVERVOLTAGE, SAG DETECT PGA3 bits GAIN[8:6] x1, x2, x4,x8, x16 VAP DSP AVGAIN[23:0] HPFDIS[23:0] HPF
REFERENCE
VOLTAGE RMS (VRMS) CALCULATION VAWV WAVEFORM SAMPLE REGISTER TOTAL ACTIVE POWER CALCULATION
VIN VN
PGA3
ADC
LPF1
VIN +0.5V/GAIN 0x5A7540= 5,928,256 ZX SIGNAL DATA RANGE 0V 0V 0x5A7540= 5,928,256 VOLTAGE CHANNEL DATA RANGE ZX DETECTION
-0.5V/GAIN ANALOG INPUT RANGE
0xA58AC0= -5,928,256 ADC OUTPUT RANGE
0V
0xA58AC0= -5,928,256
Figure 22. Voltage Channel Data Path
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to registers presented in Figure 18,
VAWV, VBWV and VCWV 24-bit signed registers are transmitted signed extended to 32 bits.
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ADE7858
The ADE7858 contains a High Speed Data Capture (HSDC) port that is specially designed to provide fast access to the waveform sample registers. See HSDC Interface section for more details.
Preliminary Technical Data
POWER QUALITY MEASUREMENTS
Zero Crossing Detection
The ADE7858 has a zero-crossing (ZX) detection circuit on the current and voltage channels. Zero-crossing events are used as a time base for various power quality measurements and in the calibration process. A zero-crossing is generated from the output of LPF1. The low pass filter is intended to eliminate all harmonics of 50Hz and 60Hz systems and help identify the zero crossing events on the fundamental components of both current and voltage channels. The digital filter has a pole at 80Hz and is clocked at 256KHz. As a result, there is a phase lag between the analog input signal (one of IA, IB, IC, VA, VB and VC) and the output of LPF1. The error in ZX detection is 0.07 for 50Hz systems (0.085 for 60Hz systems). The phase lag response of LPF1 results in a time delay of approximately 31.4 or 1.74msec (@ 50 Hz) between its input and output. The overall delay between the zero crossing on the analog inputs and ZX detection obtained after LPF1 is around 39.6 or 2.2 msec (@ 50 Hz). The ADC and HPF introduce the additional delay. The LPF1 cannot be disabled to assure a good resolution of the ZX detection. Figure 24 shows how the zerocrossing signal is detected.
REFERENCE
CHANGING PHASE VOLTAGE DATA PATH
The ADE7858 may direct one phase voltage input to the computational data path of another phase. For example, phase A voltage may be introduced in the phase B computational data path, which means all powers computed by the ADE7858 in phase B are based on phase A voltage and phase B current. Bits 9-8 (VTOIA[1:0]) of CONFIG[15:0] register manage the phase A voltage measured at VA pin. If VTOIA[1:0]=00 (default value), the voltage is directed to phase A computational data path, if VTOIA[1:0]=01, the voltage is directed to phase B path and if VTOIA[1:0]=10, the voltage is directed to phase C path. If VTOIA[1:0]=11, the ADE7858 behaves as if VTOIA[1:0]=00. Bits 11-10 (VTOIB[1:0]) of CONFIG[15:0] register manage the phase B voltage measured at VB pin. If VTOIB[1:0]=00 (default value), the voltage is directed to phase B computational data path, if VTOIB[1:0]=01, the voltage is directed to phase C path and if VTOIB[1:0]=10, the voltage is directed to phase A path. If VTOIB[1:0]=11, the ADE7858 behaves as if VTOIB[1:0]=00. Bits 13-12 (VTOIC[1:0]) of CONFIG[15:0] register manage the phase C voltage measured at VC pin. If VTOIC[1:0]=00 (default value), the voltage is directed to phase C computational data path, if VTOIC[1:0]=01, the voltage is directed to phase A path and if VTOIC[1:0]=10, the voltage is directed to phase B path. If VTOIC[1:0]=11, the ADE7858 behaves as if VTOIC[1:0]=00.
iA Phase A Computational data path VTOIA[1:0]=01, Phase A voltage directed to phase B Phase B Computational data path VTOIB[1:0]=01, Phase B voltage directed to phase C Phase C Computational data path
DSP HPFDIS[23:0]
GAIN[23:0]
HPF IA, IB, IC or VA, VB, VC PGA ADC
LPF1 ZX DETECTION
1 0.855
39.6 deg or 2.2msec @ 50Hz
ZX 0V IA, IB, IC, IN or VA, VB, VC ZX ZX ZX LPF1 output
APHCAL vA
Figure 24. Zero-Crossing Detection on Voltage and Current channels
iB
BPHCAL vB
In order to provide further protection from noise, input signals to the voltage channel with amplitude lower than 10% of full scale do not generate zero crossing events at all. The current channel ZX detection circuit is active for all input signals independent of their amplitude. The ADE7858 contains six zero crossing detection circuits, one for each phase voltage and current channel. Each circuit drives one flag in STATUS1[31:0] register. If circuit placed in phase A voltage channel detects one zero crossing event, then bit 9 (ZXVA) in STATUS1[31:0] register is set to 1. Similarly, phase B voltage circuit drives bit 10 (ZXVB), phase C voltage circuit drives bit 11 (ZXVC) and circuits placed in the current channel drive bit 12 (ZXIA), bit 13 (ZXIB) and bit 14 (ZXIC). If a ZX detection bit is set in the MASK1[31:0] register, the
iC
CPHCAL vC
VTOIC[1:0]=01, Phase C voltage directed to phase A
Figure 23.Phase voltages used in different data paths
Figure 23 presents the case in which phase A voltage is used in the phase B data path, phase B voltage is used in phase C data path and phase C voltage is used in phase A data path.
IRQ1 interrupt pin is driven low and the corresponding status
flag is set to 1. The status bit is cleared and IRQ1 pin is set back high by writing STATUS1 register with the status bit set to 1.
Rev. PrA| Page 24 of 76
Preliminary Technical Data
Zero-Crossing Timeout
Every zero-crossing detection circuit has an associated timeout register. This register is loaded with the value written into 16-bit ZXTOUT register and is decremented (1 LSB) every 62.5 s (16KHz clock). The register is reset to ZXTOUT value every time a zero crossing is detected. The default value of this register is 0xFFFF. If the timeout register decrements to 0 before a zero crossing is detected, then one of bits 8-3 of STATUS1[31:0] register is set to 1. Bit 3 (ZXTOVA), bit 4 (ZXTOVB) and bit 5 (ZXTOVC) refer to phases A, B and C of the voltage channel, bit 6 (ZXTOIA), bit 7 (ZXTOIB), bit 8 (ZXTOIC) refer to phases A, B and C of the current channel. If a ZXTOUT bit is set in the MASK1[31:0] register, the
ADE7858
status bit is cleared and IRQ1 pin is set back high by writing STATUS1 register with the status bit 19 (SEQERR) set to 1. The phase sequence error detection circuit is functional only when the ADE7858 is connected in a 3 phase 4 wire 3 voltage sensors configuration (bits 5,4 CONSEL in ACCMODE[7:0] set to 00). In all other configurations, only two voltage sensors are used and therefore it is not recommended to use the detection circuit. In these cases, the time intervals between phase voltages should be used to analyze the phase sequence (see Time Interval Between Phases section for details). Figure 26 presents the case in which phase A voltage is not followed by phase B voltage, but by phase C voltage. Every time a negative to positive zero crossing occurs, bit 19 (SEQERR) in STATUS1[31:0] register is set to 1 because such zero crossings on phase C, B or A cannot come after zero crossings from phase A, C or respectively B zero crossings.
Phase A Phase C Phase B
IRQ1 interrupt pin is driven low when the corresponding status
bit is set to 1. The status bit is cleared and IRQ1 pin is set back high by writing STATUS1 register with the status bit set to 1. The resolution of ZXOUT register is 62.5 s (16KHz clock) per LSB. Thus, the maximum time-out period for an interrupt is 4.096seconds: 216/16KHz. Figure 25 shows the mechanism of the zero-crossing timeout detection when the voltage or the current signal stays at a fixed dc level for more than 62.5 x ZXTOUT s.
16-bit INTERNAL REGISTER VALUE ZXTOUT
A,B, C Phase Voltages after LPF1
ZX A
ZX C
ZX B
Bit 19 (SEQERR) in STATUS1[31:0]
IRQ1
Voltage or Current Signal
STATUS1[19] set to 1 STATUS1[19] cancelled by a write to STATUS1[31:0] with SEQERR bit set
0V
Figure 26. SEQERR bit set to 1 when phase A voltage is followed by phase C voltage
ZXTOxy flag in STATUS1[31:0],x=V,A y=A,B,C IRQ1\ interrupt pin
Figure 25. Zero-Crossing Timeout Detection
Phase Sequence Detection
The ADE7858 has an on-chip phase sequence error detection circuit. This detection works on phase voltages and considers only the zero crossings determined by their negative to positive transitions. The regular succession of these zero crossing events is phase A followed by phase B followed by phase C (see Figure 27). If the sequence of zero crossing events is instead phase A, followed by phase C followed by phase B, then bit 19 (SEQERR) in STATUS1[31:0] register is set. If bit 19 (SEQERR) in MASK1[31:0] register is set to 1 and a phase sequence error event is triggered, then IRQ1 interrupt pin is driven low. The
Once a phase sequence error has been detected, the time measurement between various phase voltages (see Time Interval Between Phases section) may help to identify which phase voltage should be considered with another phase current in the computational data path. The bits 9-8 (VTOIA[1:0]), 11-10 (VTOIB[1:0] ) and 13-12 (VTOIC[1:0]) in CONFIG[15:0] register may be used to direct one phase voltage to the data path of another phase. See Changing Phase Voltage Data Path section for details.
Time Interval Between Phases
The ADE7858 has the capability to measure the time delay between phase voltages, between phase currents or between voltages and currents of the same phase. The negative to positive transitions identified by the zero-crossing detection circuit are used as start and stop measuring points. Only one set of such measurements are available at one time, based on bits 10, 9 (ANGLESEL[1:0]) in COMPMODE[15:0] register.
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ADE7858
Phase A Phase B Phase C
Preliminary Technical Data
voltages or phase currents are used to characterize how balanced the load is. The delays between phase voltages and currents are used to compute the power factor on each phase (see expression (5) below). 360 f Line cos x cos ANGLEx 256 KHz where x=A, B or C and fLine is 50Hz or 60Hz. (5)
ZX A
ZX B
ZX C
Phase A
Phase B
Phase C
Figure 27. Phase Sequence Detection
When ANGLESEL[1:0] bits are set to 00, the default value, then the delays between voltages and currents on the same phase are measured. The delay between phase A voltage and phase A current is stored in the 16-bit unsigned ANGLE0[15:0] register (See Figure 28 for details). In a similar way, the delays between voltages and currents on phase B and C are stored in ANGLE1[15:0] and ANGLE2[15:0] registers respectively.
ANGLE2
ANGLE1
ANGLE0
Phase A Voltage
Phase A Current
Figure 29. Delays between phase voltages (currents)
Period Measurement
The ADE7858 provides the period measurement of the line in the voltage channel. Bits 1, 0 (PERSEL[1:0]) in MMODE[7:0] register select the phase voltage used for this measurement. The PERIOD register is a 16-bit unsigned register and is updated every line period. Because of LPF1 filter (see Figure 24), a settling time of 30-40msec is associated with this filter before the measurement is stable. The period measurement has a resolution of 3.90625 s/LSB (256 KHz clock), which represents 0.0195% (50Hz/256KHz) when the line frequency is 50 Hz and 0.0234% (60Hz/256KHz) when the line frequency is 60Hz. The value of the period register for 50Hz networks is approximately 5,120 (256KHz/50Hz) and for 60Hz networks is approximately 4267 (256KHz/60Hz). The length of the register enables the measurement of line frequencies as low as 3.9 Hz (256KHz/216). The period register is stable at 1 LSB when the line is established and the measurement does not change. The following expressions may be used to compute the line period and frequency using PERIOD[15:0] register:
TL PERIOD[15 : 0] [sec] 256 E 3
ANGLE0
Figure 28.Delay between phase A voltage and current is stored in ANGLE0[15:0]
When ANGLESEL[1:0] bits are set to 01, the delays between phase voltages are measured. The delay between phase A voltage and phase C voltage is stored into ANGLE0[15:0]. The delay between phase B voltage and phase C voltage is stored in ANGLE1[15:0] register and the delay between phase A voltage and phase B voltage is stored into ANGLE2[15:0] register (see Figure 29 for details). When ANGLESEL[1:0] bits are set to 10, the delays between phase currents are measured. Similar to delays between phase voltages, the delay between phase A and phase C currents is stored into ANGLE0[15:0] register, the delay between phase B and phase C currents is stored into ANGLE1[15:0] register and the delay between phase A and phase B currents is stored into ANGLE2[15:0] register (see Figure 29 for details). The ANGLE0, ANGLE1 and ANGLE2 registers are 16-bit unsigned registers with 1LSB corresponding to 3.90625s (256 KHz clock), which means a resolution of 0.07 (360x 50Hz/256KHz) for 50Hz systems and 0.084 (360x 60Hz/256KHz) for 60Hz systems. The delays between phase
(6)
fL
256 E 3 [ Hz ] PERIOD[15 : 0]
(7)
Phase Voltage Sag Detection
The ADE7858 can be programmed to detect when the absolute value of any phase voltage drops below a certain peak value for
Rev. PrA| Page 26 of 76
Preliminary Technical Data
a number of half line cycles. The phase where this event took place is identified in bits 14, 13, 12 (VSPHASE[2:0]) of PHSTATUS[15:0] register. This condition is illustrated in Figure 30.
PHASE B VOLTAGE FULL SCALE SAGLVL[23:0]
ADE7858
Note that the internal zero-crossing counter is always active. By setting SAGLVL[23:0] register, the first sag detection result is, therefore, not done across a full SAGCYC period. Writing to the SAGCYC[7:0] register when the SAGLVL[23:0] is already initialized resets the zero-crossing counter, thus ensuring that the first sag detection result is obtained across a full SAGCYC period. The recommended procedure to manage sag events is the following: -enable SAG interrupts in MASK1[31:0] register by setting bit 16 (SAG) to 1.
SAGCYC[7:0]=0x4 PHASE A VOLTAGE FULL SCALE SAGLVL[23:0]
SAGCYC[7:0]=0x4
STATUS1[16] and PHSTATUS[12] cancelled by a write to STATUS1[31:0] with SAG bit set
-when a sag event happens, the IRQ1 interrupt pin goes low and bit 16 (SAG) in STATUS1[31:0] is set to 1. -STATUS1[31:0] register is read with bit 16 (SAG) set to 1. -PHSTATUS[15:0] is read, identifying on which phase or phases a sag event happened.
Bit 16 (SAG) in STATUS1[31:0]
IRQ1\ pin STATUS[16] and PHSTATUS[13] set to 1 VSPHASE[0]= PHSTATUS[12]
-STATUS1[31:0] register is written with bit 16 (SAG) set to 1. In this moment, bit SAG and all bits 14,13,12 (VSPHASE[2:0]) of PHSTATUS[15:0] register are erased.
VSPHASE[1]= PHSTATUS[13]
Sag Level Set
Figure 30. ADE7858 Sag Detection
Figure 30 shows phase A voltage falling below a threshold that is set in the sag level register (SAGLVL[23:0]) for four half line cycles (SAGCYC=4). When bit 16 (SAG) in STATUS1[31:0] register is set to 1 to indicate the condition, bit VSPHASE[0] in PHSTATUS[15:0] register also is set to 1 because the event happened on phase A. Bit 16 (SAG) in STATUS1[31:0] register and all bits 14,13,12 (VSPHASE[2:0]) of PHSTATUS[15:0] register (not only VSPHASE[0] bit) are erased by writing STATUS1[31:0] register with SAG bit set to 1. The SAGCYC[7:0] register represents the number of half line cycles the phase voltage must remain below the level indicated in SAGLVL register in order to trigger a sag condition. 0 is not valid a valid number for SAGCYC. For example, when the sag cycle (SAGCYC[7:0]) contains 0x07, the SAG flag in STATUS1[31:0] register is set at the end of the seventh half line cycle for which the line voltage falls below the threshold. If bit 16 (SAG) in MASK1[31:0] is set, IRQ1 interrupt pin is driven low in case of a sag event in the same moment the status bit 16 (SAG) in STATUS1[31:0] register is set to 1. The SAG status bit in STATUS1[31:0] register and all bits 14, 13, 12 (VSPHASE[2:0]) of PHSTATUS[15:0] register are cleared and
The content of the sag level register SAGLVL[23:0] is compared to the absolute value of the output from HPF. Writing 5,928,256 (0x5A7540) to SAGLVL register, puts the sag detection level at full scale - see Voltage Channel ADC Chapter, so the sag event is triggered continuously. Writing 0x00 or 0x01 puts the sag detection level at 0, so the sag event is never triggered. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the register presented in Figure 16, SAGLVL register is accessed as 32-bit registers with 8 most significant bits padded with 0s.
Peak Detection
The ADE7858 records the maximum absolute values reached by the voltage and current channels over a certain number of half line cycles and stores them into the less significant 24 bits of VPEAK[31:0] and IPEAK[31:0] 32-bit registers. PEAKCYC[7:0] register contains the number of half line cycles used as a time base for the measurement. The circuit uses the zero crossing points identified by the zero crossing detection circuit. Bits 4, 3, 2 (PEAKSEL[2:0]) in MMODE[7:0] register select on which phases the peak measurement is done. Bit 2 selects phase A, bit 3 selects phase B and bit 4 selects phase C. Selecting more than one phase to monitor the peak values decreases proportionally the measurement period indicated in PEAKCYC[7:0] register because zero crossings from more phases are involved in the process. When a new peak value is determined, one of bits 26, 25, 24 (IPPHASE[2:0] or VPPHASE[2:0]) in IPEAK[31:0] and VPEAK[31:0] registers is set to 1 identifying the phase that triggered the peak detection event. For example, if a peak value has been identified on phase A current, bit 24 (IPPHASE[0]) in IPEAK[31:0] register is set to 1. If next time a new peak value is measured on phase B, then
IRQ1 pin is set back high by writing STATUS1[31:0] register with the status bit set to 1.
When the phase B voltage falls below the threshold indicated into SAGLVL[23:0] register for two line cycles, bit VSPHASE[1] in PHSTATUS[15:0] register is set to 1 and bit VSPHASE[0] is cleared to 0. In the same moment, bit 16 (SAG) in STATUS1[31:0] register is set to 1 to indicate the condition.
Rev. PrA | Page 27 of 76
ADE7858
bit 24 (IPPHASE[0]) of IPEAK[31:0] is cleared to 0 and bit 25 (IPPHASE[1]) of IPEAK[31:0] is set to 1. Figure 31 presents the composition of IPEAK and VPEAK registers.
IPPHASE/ VPPHASE bits 31 27 26 25 24 23 0 24 bit unsigned number 00000 peak detected on phase C peak detected on phase B
Figure 31.Composition of IPEAK[31:0] and VPEAK[31:0] registers
Peak value written into IPEAK at the end of first PEAKCYC period End of first PEAKCYC=16 period End of second PEAKCYC=16 period
Preliminary Technical Data
in STATUS1[31:0] is set to 1. In a similar way, at the end of the peak detection period in the voltage channel, bit 24 (PKV) in STATUS1[31:0] register is set to 1. If bit 24 (PKV) in MASK1[31:0] register is set, then IRQ1 interrupt pin is driven low at the end of PEAKCYC period and the status bit 24 (PKV) in STATUS1[31:0] is set to 1. To find the phase that triggered the interrupt, one of IPEAK[31:0] or VPEAK[31:0] registers is read immediately after reading STATUS1[31:0]. Then the status bits are cleared and IRQ1 pin is set back high by writing STATUS1[31:0] register with the status bit set to 1. Note that the internal zero-crossing counter is always active. By setting bits 4, 3, 2 (PEAKSEL[2:0]) in MMODE[7:0] register, the first peak detection result is, therefore, not done across a full PEAKCYC period. Writing to the PEAKCYC[7:0] register when the PEAKSEL[2:0] bits are set resets the zero-crossing counter, thus ensuring that the first peak detection result is obtained across a full PEAKCYC period.
peak detected on phase A
Phase A current
Overvoltage and Overcurrent Detection
Phase A Voltage Channel
Bit 24 of IPEAK cleared to 0 at the end of second PEAKCYC period
Overvoltage detected
OVLVL[23:0]
Bit 24 of IPEAK
Phase B current
Bit 25 of IPEAK
Peak value written into IPEAK at the end of second PEAKCYC period
Bit 25 of IPEAK set to 1 at the end of second PEAKCYC period
Bit 18 (OV) of STATUS1 STATUS1[18] and PHSTATUS[9] cancelled by a write of STATUS1 with OV bit set
Figure 32. ADE7858 Peak Level Detection
Figure 32 shows how the ADE7858 records the peak value on the current channel when measurements on phases A and B are enabled (bits PEAKSEL[2:0] in MMODE[7:0] are 011). PEAKCYC[7:0] is set to 16, meaning that the peak measurement cycle is 4 line periods. The maximum absolute value of phase A is the greatest during the first 4 line periods (PEAKCYC=16), so the maximum absolute value is written into the less significant 24 bits of IPEAK[31:0] register and bit 24 (IPPHASE[0]) of IPEAK[31:0] register is set to 1 at the end of the period. This bit remains 1 for the duration of the second PEAKCYC period of 4 line cycles. The maximum absolute value of phase B is the greatest during the second PEAKCYC period, so the maximum absolute value is written into the less significant 24 bits of IPEAK register and bit 25 (IPPHASE[1]) in IPEAK register is set to 1 at the end of the period. At the end of the peak detection period in the current channel, bit 23 (PKI) in STATUS1[31:0] register is set to 1. If bit 23 (PKI) in MASK1[31:0] register is set, then IRQ1 interrupt pin is driven low at the end of PEAKCYC period and the status bit 23 (PKI)
Bit 9 (OVPHASE) of PHSTATUS
Figure 33. ADE7858 Overvoltage Detection
The ADE7858 detects when the instantaneous absolute value measured on the voltage and current channels becomes greater than thresholds set in OVLVL[23:0] and OILVL[23:0] 24-bit unsigned registers. If bit 18 (OV) in MASK1[31:0] register is set, IRQ1 interrupt pin is driven low in case of an overvoltage event. There are two status flags set when IRQ1 interrupt pin is driven low: bit 18 (OV) in STATUS1[31:0] register and one of bits 11, 10, 9 (OVPHASE[2:0]) in PHSTATUS[15:0] register identifying the phase that generated the overvoltage. The status bit 18 (OV) in STATUS1[31:0] register and all bits 11, 10, 9 (OVPHASE[2:0]) in PHSTATUS[15:0] register are cleared and
IRQ1 pin is set back high by writing STATUS1[31:0] register with the status bit set to 1. Figure 33 presents overvoltage detection in phase A voltage. Whenever the absolute instantaneous value of the voltage goes above the threshold
Rev. PrA| Page 28 of 76
Preliminary Technical Data
from OVLVL[23:0] register, bit 18 (OV) in STATUS1[31:0] and bit 9 (OVPHASE[0]) in PHSTATUS[15:0] registers are set to 1. The bit 18 (OV) of STATUS1[31:0] register and bit 9 (OVPHASE[0]) in PHSTATUS[15:0] register are cancelled when STATUS1 register is written with bit 18 (OV) set to 1. The recommended procedure to manage overvoltage events is the following: -enable OV interrupts in MASK1[31:0] register by setting bit 18 (OV) to 1. -when an overvoltage event happens, the IRQ1 interrupt pin goes low. -STATUS1[31:0] register is read with bit 18 (OV) set to 1. -PHSTATUS[15:0] is read, identifying on which phase or phases an overvoltage event happened. -STATUS1[31:0] register is written with bit 18 (OV) set to 1. In this moment, bit OV is erased and also all bits 11, 10, 9 (OVPHASE[2:0]) of PHSTATUS[15:0] register. In case of an overcurrent event, if bit 17 (OI) in MASK1[31:0] register is set, IRQ1 interrupt pin is driven low. In the same moment, bit 17 (OI) in STATUS1[31:0] register and one of bits 5, 4, 3 (OIPHASE[2:0]) in PHSTATUS[15:0] register identifying the phase that generated the interrupt are set. To find the phase that triggered the interrupt, PHSTATUS[15:0] register is read immediately after reading STATUS1[31:0]. Then the status bit 17 (OI) in STATUS1[31:0] register and bits 5,4,3 (OIPHASE[2:0]) in PHSTATUS[15:0] register are cleared and
ADE7858
phase errors. For example, a current transformer (CT) with a phase error of 0.1 to 3 is not uncommon. These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7858 provides a means of digitally calibrating these small phase errors. The ADE7858 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. The phase calibration registers (APHCAL[9:0], BPHCAL[9:0], and CPHCAL[9:0]) are 10-bit registers that can vary the time advance in the voltage channel signal path from +61.5 s to -374.0 s, respectively. Negative values written to the PHCAL registers represent a time advance, and positive values represent a time delay. One LSB is equivalent to 0.976 s of time delay or time advance (clock rate of 1.024MHz). With a line frequency of 60 Hz, this gives a phase resolution of 0.0211 (360 x 60 Hz/1.024 MHz) at the fundamental. This corresponds to a total correction range of -8.079 to +1.329 at 60 Hz. At 50Hz, the correction range is -6.732 to +1.107 and the resolution is 0.0176(360 x 50 Hz/1.024 MHz) . Given a phase error of x degrees measured using the phase voltage as the reference, then the corresponding LSBs are computed dividing x by the phase resolution (0.0211/LSB for 60Hz, 0.0176/LSB for 50Hz). Only results between -383 and +63 are acceptable. Numbers outside this range are not accepted. If the result is negative, the absolute value is written into PHCAL registers. If the result is positive, 512 is added to it before writing the result into PHCAL.
IRQ1 pin is set back high by writing STATUS1[31:0] register with the status bit set to 1. The process is similar with the overvoltage detection.
Overvoltage and Overcurrent Level Set
The content of the overvoltage OVLVL[23:0] and overcurrent OILVL[23:0] 24-bit unsigned registers is compared to the absolute value of the voltage and current channels. The maximum value of these registers is the maximum value of the HPF outputs: +5,928,256 (0x5A7540). When OVLVL or OILVL are equal to this value, the overvoltage or overcurrent conditions will never be detected. Writing 0x0 to these registers signifies the overvoltage or overcurrent conditions are continuously detected and the corresponding interrupts are triggered permanently. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the register presented in Figure 16, OILVL and OVLVL registers are accessed as 32-bit registers with 8 most significant bits padded with 0s.
x ,x 0 phase _ resolution yPHCAL x 512, x 0 phase _ resolution
(8)
Figure 35 illustrates how the phase compensation is used to remove x=-1 phase lead in IA of the current channel from the external current transducer (equivalent of 55.5s for 50Hz systems). To cancel the lead (1) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. Using expression (8), APHCAL is 57, rounded up from 56.8. The phase lead is achieved by introducing a time delay of 55.73 s into the phase A current. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. As presented in Figure 34, APHCAL, BPHCAL and CPHCAL 10-bit registers are accessed as a 16-bit registers with 6 most significant bits padded with 0s.
PHASE COMPENSATION
As seen in Current Channel ADC and Voltage Channel ADC chapters, the data path for both current and voltages is the same. The phase error between current and voltage signals introduced by the ADE7858 is negligible. However, the ADE7858 must work with transducers that may have inherent
15 0000 00
10
9 xPHCAL
0
Figure 34. xPHCAL registers (x=A,B,C) are communicated as 16-bit registers
Rev. PrA | Page 29 of 76
ADE7858
IAP
Preliminary Technical Data
IA IAN
PGA1
ADC
Phase Calibration APHCAL=57
VAP
VA VN
PGA3
ADC
IA
1
IA
Phase compensation achieved delaying IA by 56us
VA
VA 50Hz
Figure 35. Phase Calibration on Voltage Channels
REFERENCE CIRCUIT
The nominal reference voltage at the REFIN/OUT pin is 1.21% V. This is the reference voltage used for the ADCs in the ADE7858. The REFIN/OUT pin can be overdriven by an external source, for example, an external 1.2 V reference. The voltage of the ADE7858 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/C). The value of the temperature drift varies from part to part. Because the reference is used for all ADCs, any x% drift in the reference results in a 2x% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter. Alternatively, the meter can be calibrated at multiple temperatures. If bit 0 (EXTREFEN) in CONFIG2[7:0] register is cleared to 0 (the default value), the ADE7858 uses the internal voltage reference. If the bit is set to 1, then the external voltage reference is used. CONFIG2 register should be set during PSM0 mode. Its value is maintained during the PSM3 power mode.
by setting bit 17 (DREADY) to 1 in STATUS0[31:0] register. An interrupt attached to this flag may be enabled by setting bit 17 (DREADY) in MASK0[31:0] register. If enabled, the IRQ0 pin is set low and status bit DREADY is set to 1 at the end of the computations. The status bit is cleared and IRQ0 pin is set back high by writing STATUS0[31:0] register with bit 17 (DREADY) set to 1. The registers used by the DSP are located in the data memory RAM, at addresses between 0x4000 and 0x43FF. The width of this memory is 28 bits. As seen in Power Up Procedure section, at power up or after a hardware or software reset, the DSP is in idle mode. No instruction is being executed. All the registers located in the data memory RAM are initialized at 0, their default values. The register RUN[15:0] used to start and stop the DSP is cleared to 0x0000. The RUN[15:0] register needs to be written with 0x0001 in order for the DSP to start code execution. It is recommended to first initialize all ADE7858 registers located into the data memory RAM with their desired values and then write RUN[15:0] register with 0x0001. In this way, the DSP starts the computations from a desired configuration. There is no obvious reason to stop the DSP if the ADE7858 is maintained in PSM0 normal mode. All ADE7858 registers including ones located in the data memory RAM can be modified without stopping the DSP. However, to stop the DSP, 0x0000 has to be written into the register RUN[15:0]. To start the DSP again, one of the following procedures must be followed:
DIGITAL SIGNAL PROCESSOR
The ADE7858 contains a fixed function Digital Signal Processor (DSP) that computes all powers and rms values. It contains various memories: program memory ROM, program memory RAM, data memory RAM. The program used for the power and rms computations is stored in the program memory ROM and the processor executes it every 8KHz. The end of the computations is signaled
Rev. PrA| Page 30 of 76
Preliminary Technical Data
- if ADE7858 registers located in the data memory RAM have not been modified, write 0x0001 into register RUN[15:0] to start the DSP. -if ADE7858 registers located in the data memory RAM have to be modified, first execute a software or a hardware reset, initialize all ADE7858 registers at desired values and then write 0x0001 into register RUN[15:0] to start the DSP. As mentioned in Power Management chapter, when the ADE7858 switches out of PSM0 power mode, it is recommended to stop the DSP by writing 0x0000 into RUN[15:0] register (see Table 9 for recommended actions when changing power modes).
ADE7858
The rms calculation based on this method is simultaneously processed on all seven analog input channels. Each result is available in 24-bit registers AIRMS, BIRMS, CIRMS, AVRMS, BVRMS and CVRMS.
Current RMS Calculation
This chapter presents the first approach to compute the rms values of all phase currents. Figure 36 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. The current channel rms value is processed from the samples used in the current channel. The current rms values are signed 24-bit values and they are stored into AIRMS[23:0], BIRMS[23:0] and CIRMS[23:0]. The update rate of the current rms measurement is 8KHz.
xIRMSOS[23:0]
ROOT MEAN SQUARE MEASUREMENT
Root mean square (rms) is a measurement of the magnitude of an ac signal. Its definition can be both practical and mathematical. Defined practically, the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load. Mathematically, the rms value of a continuous signal f(t) is defined as
27 CURRENT SIGNAL FROM HPF OR INTEGRATOR (IF ENABLED) LPF x2
xIRMS[23:0]
FRMS
1 T
0
T
f 2 t dt
(9)
0x5A7540= 5,928,256
For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. 1 FRMS N
0V
n1
f
N
0xA58AC0= -5,928,256
2
[n]
(10)
Figure 36. Current RMS Signal Processing
The expression (10) implies that for signals containing harmonics, the rms calculation contains the contribution of all harmonics, not only the fundamental. The method is to lowpass filter the square of the input signal (LPF) and take the square root of the result (see Figure 36).
f (t )
F
k 1
k
2 sin kt k
(11)
With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately 5,928,256. The equivalent rms value of a full-scale sinusoidal signal is 4,191,910(0x3FF6A6), independent of the line frequency. If the integrator is enabled, that is when bit 0 (INTEN) in CONFIG[15:0] register is set to 1, the equivalent rms value of a full-scale sinusoidal signal at 50Hz is 4,191,910(0x3FF6A6) and at 60Hz is 3,493,258(0x354D8A). The accuracy of the current rms is typically 0.1% error from the full-scale input down to 1/1000 of the full-scale input. Additionally, this measurement has a bandwidth of 2 kHz. It is recommended to read the rms registers synchronous to the voltage zero
Then
f 2 (t )
k 1
Fk2
F
k 1
2 k cos(2kt
k )
(12)
2
k ,m 1 k m
2 F
k
Fm sin kt k sin mt m
crossings to ensure stability. The IRQ1 interrupt can be used to indicate when a zero crossing has occurred (see the Interrupts section). Table 10 shows the settling time for the IRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel.
Table 10. Settling Time for IRMS Measurement
Integrator Off Integrator On 50Hz Input signals 530msec 550msec 60Hz Input signals 530msec 500msec
After the LPF and the execution of the square root, the rms value of f(t) is obtained:
F
F
k 1
2 k
(13)
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the register presented in Figure
Rev. PrA | Page 31 of 76
ADE7858
16, AIRMS, BIRMS and CIRMS 24-bit signed registers are accessed as 32-bit registers with 8 most significant bits padded with 0s.
Preliminary Technical Data
this measurement has a bandwidth of 2 kHz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ1 interrupt can be used to indicate when a zero crossing has occurred (see the Interrupts section).
xVRMSOS[23:0]
Current RMS Offset Compensation
The ADE7858 incorporates a current rms offset compensation register for each phase: AIRMSOS[23:0], BIRMSOS[23:0] and CIRMSOS[23:0]. These are 24-bit signed registers and are used to remove offsets in the current rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of I2(t). One LSB of the current rms offset compensation register is equivalent to one LSB of the current rms register. Assuming that the maximum value from the current rms calculation is 4,191,400 with full-scale ac inputs (50 Hz), one LSB of the current rms offset represents 0.00037% ( 41912 128 / 4191 1 100 ) of the rms measurement at 60 dB down from full scale. Calibration of the offset should be done at low current and values at zero input should be ignored.
2 IRMS IRMS 0 128 IRMSOS
27 LPF VOLTAGE SIGNAL FROM HPF x2
xVRMS[23:0]
0x5A7540= 5,928,256
0V
0xA58AC0= -5,928,256
Figure 37. Voltage RMS Signal Processing
(14)
Table 11 shows the settling time for the VRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the voltage channel.
Table 11. Settling Time for VRMS Measurement
50Hz Input signals 530 ms 60Hz Input signals 530 ms
where IRMS0 is the rms measurement without offset correction. Note that at low currents, certain negative offset values of IRMSOS may determine a negative square root argument in expression (14). As the square root circuit requires positive arguments only, the result of the square root operation is erroneous, equal to 0x7FFFFF. It is recommended to avoid using big, negative IRMSOS values and as the equivalent rms value of a full-scale sinusoidal signal is 4,191,910(0x3FF6A6), much smaller than 0x7FFFFF, such values may be easily eliminated from consideration. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to the register presented in Figure 15, AIRMSOS, BIRMSOS and CIRMSOS 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the register presented in Figure 16, AVRMS, BVRMS and CVRMS 24-bit signed registers are accessed as 32-bit registers with 8 most significant bits padded with 0s.
Voltage RMS Offset Compensation
The ADE7858 incorporates a voltage rms offset compensation for each phase AVRMSOS[23:0], BVRMSOS[23:0], and CVRMSOS[23:0]. These are 24-bit signed registers used to remove offsets in the voltage rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). One LSB of the voltage rms offset compensation register is equivalent to one LSB of the voltage rms register. Assuming that the maximum value from the voltage rms calculation is 4,191,400 with full-scale ac inputs (50 Hz), one LSB of the current rms offset represents 0.00037% ( 41912 128 / 4191 1 100 ) of the rms measurement at 60 dB down from full scale. Calibration of the offset should be done at low current and values at zero input should be ignored.
2 VRMS VRMS 0 128 VRMSOS
Voltage Channel RMS Calculation
Figure 37 shows the detail of the signal processing chain for the rms calculation on one of the phases of the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel. The voltage rms values are signed 24-bit values and they are stored into the registers AVRMS[23:0], BVRMS[23:0] and CVRMS[23:0]. The update rate of the current rms measurement is 8KHz. With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately 5,928,256. The equivalent rms value of a full-scale sinusoidal signal is 4,191,910 (0x3FF6A6), independent of the line frequency. The accuracy of the voltage rms is typically 0.1% error from the full-scale input down to 1/1000 of the full-scale input. Additionally,
(15)
where VRMS0 is the rms measurement without offset correction. Note that at low currents, certain negative offset values of VRMSOS may determine a negative square root argument in expression (15). As the square root circuit requires positive
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Preliminary Technical Data
arguments only, the result of the square root operation is erroneous, equal to 0x7FFFFF. It is recommended to avoid using big, negative VRMSOS values and as the equivalent rms value of a full-scale sinusoidal signal is 4,191,910(0x3FF6A6), much smaller than 0x7FFFFF, such values may be easily eliminated from consideration. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVRMSOS, BVRMSOS and CVRMSOS 24-bit registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
ADE7858
k 1
Vk Ik cosk k . This is the expression used to calculate
the total active power in the ADE7858 for each phase. Figure 38 shows how the ADE7858 computes the total active power on each phase. First, it multiplies the current and voltage signals in each phase. Then, extracts the dc component of the instantaneous power signal in each phase (A, B and C) using LPF2, the low pass filter.
AIGAIN Digital HPFDIS[23:0] Integrator HPF iA AWATTOS LPF APHCAL AWGAIN INSTANTANEOUS PHASE A ACTIVE POWER
ACTIVE POWER CALCULATION
The ADE7858 computes the total active power on every phase. Total active power considers in its calculation all fundamental and harmonic components of the voltages and currents.
vA
HPFDIS[23:0] HPF
AVGAIN Digital Signal Processor
Total Active Power Calculation
Electrical power is defined as the rate of energy flow from source to load. It is given by the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. If an ac system is supplied by a voltage v(t) and consumes the current i(t) and each of them contains harmonics, then:
v (t) Vk 2 sinkt k
k 1
Figure 38. Total Active Power Data Path
If the phase currents and voltages contain only the fundamental component, are in phase (that is 1 1 0 ) and they correspond to full scale ADC inputs, then multiplying them results in an instantaneous power signal that has a dc component V1 I1 and a sinusoidal component V1 I1 cos2t . Figure 39 shows the corresponding waveforms.
0x3FED4D6 = 67,032,278 INSTANTANEOUS POWER SIGNAL p(t)=VRMS x IRMS - VRMS x IRMS x cos(2wt) INSTANTANEOUS ACTIVE POWER SIGNAL: VRMS x IRMS
(16)
VRMS x IRMS 0x1FF6A6B = 33,516,139
i(t) I k 2 sinkt k
k 1
where Vk , I k = rms voltage and current of each harmonic, k , k =phase delays of each harmonic. The instantaneous power in an ac system is:
p(t) v (t) i(t) Vk I k cos k k Vk I k cos2kt k k
k 1 k 1
0x000 0000
i(t) 2 IRMS sin(t) v (t ) 2 VRMS sin(t )
Figure 39. Active Power Calculation

Vk I m cosk m t k m cosk m t k m
k ,m 1 k m
(17)
The average power over an integral number of line cycles (n) is given by the expression in Equation (18).
Because LPF2 does not have an ideal brick wall frequency response (see Figure 40), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated over time to calculate the energy.
P
1 nT p t dt Vk I k cos k k nT 0 k 1
(18)
where: T is the line cycle period. P is referred to as the total active or total real power. Note that the total active power is equal to the dc component of the instantaneous power signal p(t) in expression (17), that is,
Rev. PrA | Page 33 of 76
ADE7858
0
Preliminary Technical Data
CWGAIN 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
-5
Active Power Offset Calibration
The ADE7858 also incorporates a watt offset 24-bit register on each phase and on each active power. AWATTOS[23:0], BWATTOS[23:0], and CWATTOS[23:0] registers compensate the offsets in the total active power calculations. These are signed twos complement, 24-bit registers that are used to remove offsets in the active power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. One LSB in the active power offset register is equivalent to 1 LSB in the active power multiplier output. With full scale current and voltage inputs, the LPF2 output is PMAX=33,516,139. At -80dB down from the full scale (active power scaled down 104 times), one LSB of the active power offset register represents 0.032% of PMAX. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AWATTOS, BWATTOS, CWATTOS 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
-10
-15
-20
-25 0.1
1
3
10
Figure 40. Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase
The ADE7858 stores the instantaneous total phase active powers into AWATT[23:0], BWATT[23:0] and CWATT[23:0] registers. Their expression is:
xWATT
Uk Ik 1 cos k k PMAX 4 U FS I FS 2 k 1
(19)
where: x=A, B, C, UFS, IFS are the rms values of the phase voltage and current when the ADC inputs are at full scale. PMAX=33,516,139 is the instantaneous power computed when the ADC inputs are at full scale and in phase. The xWATT[23:0], x=A, B, C waveform registers may be accessed using various serial ports. Refer to Waveform Sampling Mode chapter for more details.
Sign of Active Power Calculation
Note that the average active power is a signed calculation. If the phase difference between the current and voltage waveform is more than 90, the average power becomes negative. Negative power indicates that energy is being injected back on the grid. The ADE7858 has a sign detection circuitry for total active power calculations. As will be seen in the Active Energy Calculation section, the active energy accumulation is performed in two stages. Every time a sign change is detected in the energy accumulation at the end of the first stage, that is after the energy accumulated into the internal accumulator reaches WTHR[47:0] threshold, a dedicated interrupt is triggered. The sign of each phase active power may be read in PHSIGN[15:0] register. Bits 8, 7, 6 (REVAPC, REVAPB and respectively REVAPA) in STATUS0[31:0] are set when a sign change occurs in the corresponding phase total active power. Bits 2, 1, 0 (CWSIGN, BWSIGN and respectively AWSIGN) in PHSIGN[15:0] register are set simultaneously with REVAPC, REVAPB and REVAPA bits. They indicate the sign of the power. When they are 0, the corresponding power is positive. When they are 1, the corresponding power is negative. Bit REVAPx of STATUS0[31:0] and bit xWSIGN in PHSIGN[15:0] refer to the total active power of phase x, x=A,B or C. Interrupts attached to the bits 8, 7, 6 (REVAPC, REVAPB and respectively REVAPA) in STATUS0[31:0] register may be
Active Power Gain Calibration
Note that the average active power result from the LPF2 output in each phase can be scaled by 100% by writing to the phase's watt gain 24-bit register (AWGAIN[23:0], BWGAIN[23:0], CWGAIN[23:0]). xWGAIN, x=A,B,C registers are placed in each phase of the total active power data path. The watt gain registers are twos complement, signed registers and have a resolution of 2-23/LSB. Equation (20) describes mathematically the function of the watt gain registers. Average Power Data Watt Gain Register LPF2 Output 1 2 23
(20)
The output is scaled by -50% by writing 0xC00000 to the watt gain registers and increased by +50% by writing 0x400000 to them. These registers can be used to calibrate the active power (or energy) calculation in the ADE7858 for each phase. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AWGAIN, BWGAIN,
Rev. PrA| Page 34 of 76
Preliminary Technical Data
enabled by setting bits 8, 7, 6 in MASK0[31:0] register. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever a change of sign occurs. To find the phase that triggered the interrupt, PHSIGN[15:0] register is read immediately after reading STATUS0[31:0]. Then the status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1.
ADE7858
Active Energy Calculation
As previously stated, power is defined as the rate of energy flow. This relationship can be expressed mathematically as
Power dEnergy dt
(21)
Conversely, Energy is given as the integral of power.
Energy p t dt
(22)
AIGAIN
Digital HPFDIS[23:0] Integrator HPF REVAPA bit in STATUS0[31:0] AWATTOS LPF AWGAIN AWATTHR[31:0]
iA
APHCAL
HPFDIS[23:0] HPF
ACCUMULATOR
WTHR[47:0]
32 bit register
vA
AVGAIN Digital Signal Processor
Figure 41. ADE7858 Total Active Energy Accumulation
Total active energy accumulation is always a signed operation. Negative energy is subtracted from the active energy contents. The ADE7858 achieves the integration of the active power signal in two stages (see Figure 41). The first stage is done inside the DSP: every 125sec (8KHz frequency), the instantaneous phase total active power is accumulated into an internal register. When a threshold is reached, a pulse is generated at processor port and the threshold is subtracted from the internal register. The sign of the energy in this moment is considered the sign of the active power (see Sign of Active Power Calculation section for details). The second stage is done outside the DSP and consists in accumulating the pulses generated by the processor into internal 32-bit accumulation registers. The content of these registers is transferred to watthr registers xWATTHR[31:0], x=A,B,C when these registers are accessed.
WTHR[47:0]
Let's suppose a derivative of wh [10n wh], n an integer, is desired as 1LSB of WATTHR. Then WTHR is computed using the following expression:
WTHR where:
PMAX f s 3600 10 n U FS I FS
(23)
PMAX=33,516,139=0x1FF6A6B is the instantaneous power computed when the ADC inputs are at full scale. fs=8KHz is the frequency with which the DSP computes the instantaneous power. UFS, IFS are the rms values of phase voltages and currents when the ADC inputs are at full scale. The maximum value that may be written on WTHR[47:0] is 247-1. The minimum value is 0x0, but it is recommended to write a number equal or greater than PMAX. Negative numbers should never be used. The WTHR[47:0] is a 48-bit register. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. As presented in Figure 43, WTHR register is accessed as two 32-bit registers (WTHR1[31:0] and WTHR0[31:0]), each having 8 most significant bits padded with 0s.
active power accumulation in DSP
DSP generated pulses 1 DSP pulse = 1LSB of WATTHR[47:0]
Figure 42. Active Power Accumulation inside DSP
Figure 42 explains this process. The WTHR[47:0] 48-bit signed register contains the threshold. It is introduced by the user and is common for all phase total active powers. Its value depends on how much energy is assigned to 1LSB of watt-hour registers.
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ADE7858
WTHR[47:0] 47 24 23 0
Preliminary Technical Data
The maximum value that can be stored in the watt-hr accumulation register before it overflows is 231 - 1 or 0x7FFFFFFF. The integration time is calculated as
Time 0 x7FFF, FFFF 125s 74h33 min 55s
31 0000 0000 24 23 24 bit signed number 0 31 0000 0000 24 23 0 24 bit unsigned number
(25)
Energy Accumulation Modes
The active power accumulated in each watt-hr accumulation 32-bit register (AWATTHR, BWATTHR, CWATTHR) depends on the configuration of bits 5, 4 (CONSEL) in ACCMODE[7:0] register. The different configurations are described in Table 12.
Table 12. Inputs to Watt-Hr Accumulation Registers
CONSEL 00 01 10 11 AWATTHR VA x IA VA x IA VA x IA VA x IA BWATTHR VB x IB 0 VB x IB VB = -VA - VC VB x IB VB = -VA CWATTHR VC x IC VC x IC VC x IC VC x IC
WTHR1[31:0]
WTHR0[31:0]
Figure 43. WTHR[47:0] is communicated as two 32-bit registers
This discrete time accumulation or summation is equivalent to integration in continuous time following the description in expression (24).
Energy p t dt Lim p nT T T 0 n 0
(24)
where:
n is the discrete time sample number. T is the sample period.
In the ADE7858, the total phase active powers are accumulated in AWATTHR[31:0], BWATTHR[31:0] and CWATTHR[31:0] 32-bit signed registers. The active energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the active power is positive. Conversely, if the active power is negative, the energy register would underflow to full-scale positive (0x7FFFFFFF) and continue decreasing in value. Bit 0 (AEHF) in STATUS0[31:0] register is set when bit 30 of one of xWATTHR, x=A, B, C registers changes, signifying one of these registers is half full. If the active power is positive, the watt-hr register becomes half full when it increments from 0x3FFF FFFF to 0x4000 0000. If the active power is negative, the watt-hr register becomes half full when it decrements from 0xC000 0000 to 0xBFFF FFFF. Setting bit 0 in MASK0[31:0] register enables the AEHF interrupt. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever one of the energy registers xWATTHR (for AEHF interrupt), x=A,B,C becomes half full. The status bit is cleared and IRQ0 pin is set to logic high by writing STATUS0 register with the corresponding bit set to 1. Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a read-with-reset for all watt-hr accumulation registers, that is, the registers are reset to 0 after a read operation.
Depending on the poly-phase meter service, the appropriate formula should be chosen to calculate the active energy. The American ANSI C12.10 Standard defines the different configurations of the meter. Table 13 describes which mode should be chosen in these different configurations.
Table 13. Meter Form Configuration
ANSI Meter Form 5S/13S 3-Wire Delta 6S/14S 4-Wire Wye 8S/15S 4-Wire Delta 9S/16S 4-Wire Wye CONSEL 01 10 11 00
Bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register determine how CF frequency output may be generated function of the total and fundamental active powers. While the watt-hr accumulation registers accumulate the active power in a signed format, the frequency output may be generated in signed mode or in absolute mode, function of WATTACC[1:0]. See Energy to Frequency Conversion chapter for details.
Line Cycle Active Energy Accumulation Mode
In line cycle energy accumulation mode, the energy accumulation is synchronized to the voltage channel zero crossings so that active energy is accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation and allows the energy to be accumulated accurately over a shorter time. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. In line cycle energy accumulation mode, the ADE7858 transfers the active energy accumulated in the 32-bit internal accumulation registers into xWATHHR[31:0], x=A,B,C registers after an integral number of
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register is 125s (1/8KHz). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x00000, the average word value from each LPF2 is PMAX=33,516,139=0x1FF6A6B. If the WTHR[47:0] threshold is set at PMAX level, this means the DSP generates a pulse that is added at watt-hr registers every 125 s.
Rev. PrA| Page 36 of 76
Preliminary Technical Data
line cycles, as shown in Figure 44. The number of half line cycles is specified in the LINECYC[15:0] register.
ZXSEL[0] in LCYCMODE[7:0]
ADE7858
Therefore, total energy accumulated using the line-cycle accumulation mode is e p t dt nT Vk I k cos k k
t k 1 t nT
(26)
ZERO CROSSING DETECTION (PHASE A) ZXSEL[1] in LCYCMODE[7:0] LINECYC[15:0]
where nT is the accumulation time. Note that line cycle active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two methods is equivalent.
ZERO CROSSING DETECTION (PHASE B) ZXSEL[2] in LCYCMODE[7:0]
CALIBRATION CONTROL
ZERO CROSSING DETECTION (PHASE C)
REACTIVE POWER CALCULATION
AWGAIN AWATTHR[31:0]
AWATTOS
OUTPUT FROM LPF
The ADE7858 computes the total reactive power on every phase. Total reactive power integrates all fundamental and harmonic components of the voltages and currents. A load that contains a reactive element (inductor or capacitor) produces a phase difference between the applied ac voltage and the resulting current. The power associated with reactive elements is called reactive power, and its unit is VAR. Reactive power is defined as the product of the voltage and current waveforms when all harmonic components of one of these signals are phase shifted by 90. Expression (29) gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90. v (t) Vk 2 sinkt k
k 1
ACCUMULATOR
WTHR[47:0]
32 bit register
Figure 44. ADE7858 Line Cycle Active Energy Accumulation Mode
The line cycle energy accumulation mode is activated by setting bit 0 (LWATT) in the LCYCMODE[7:0] register. The energy accumulation over an integer number of half line cycles is written to the watt-hr accumulation registers after LINECYC[15:0] number of half line cycles are detected. When using the line cycle accumulation mode, the bit 6 (RSTREAD) of the LCYCMODE[7:0] register should be set to Logic 0 because the read with reset of watt-hr registers is not available in this mode. Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting bits 5, 4, 3 (ZXSEL) in the LCYCMODE[7:0] register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration. The number of zero crossings is specified by the LINECYC[15:0] 16-bit unsigned register. The ADE7858 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero-crossing counter is always active. By setting bit 0 (LWATT) in LCYCMODE[7:0] register, the first energy accumulation result is, therefore, incorrect. Writing to the LINECYC[15:0] register when the LWATT bit is set resets the zero-crossing counter, thus ensuring that the first energy accumulation result is accurate. At the end of an energy calibration cycle, the bit 5 (LENERGY) in the STATUS0[31:0]register is set. If the corresponding mask bit in the MASK0[31:0] interrupt mask register is enabled, the IRQ0 pin also goes active low. The status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1. Because the active power is integrated on an integer number of half-line cycles in this mode, the sinusoidal components are reduced to 0, eliminating any ripple in the energy calculation.
(27)
i(t) I k 2 sinkt k
k 1
(28)
i' (t) I k 2 sin kt k 2 k 1
i t is the current waveform with all harmonic components phase shifted by 90. Then the instantaneous reactive power q(t) can be expressed as q t v t i t
q(t) Vk I k 2 sinkt k sin kt k 2 k 1 Vk I m 2 sinkt k sin mt m 2 k ,m 1
k m
(29)
Note that q(t) can be rewritten as
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ADE7858
q(t) Vk I k cos k k cos 2kt k k 2 2 k 1 Vk I m cos k m t k k 2 k ,m 1 k m Vk I m cos k m t k k 2 k ,m 1 k m
Preliminary Technical Data
CFVARGAIN[23:0]). xVARGAIN, x=A,B,C registers are placed in each phase of the total reactive power data path. The VAR gain registers are twos complement, signed registers and have a resolution of 2-23/LSB. The function of the VAR gain registers is expressed by Average Reactive Power VAR Gain Register LPF2 Output 1 2 23
(30) (33)
The average total reactive power over an integral number of line cycles (n) is given by the expression in Equation (31). Q
1 nT q t dt Vk I k cos k k nT 0 2 k 1
The output is scaled by -50% by writing 0xC00000 to the VAR gain registers and increased by +50% by writing 0x400000 to them. These registers can be used to calibrate the reactive power (or energy) gain in the ADE7858 for each phase. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVARGAIN, BVARGAIN, CVARGAIN 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
(31)
Q Vk I k sin k k
k 1
where: T is the period of the line cycle. Q is referred to as the total reactive power. Note that the total reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation (30), that is, Vk I k sin k k . This is the relationship used to
k 1
Reactive Power Offset Calibration
The ADE7858 provides a VAR offset register on each phase and on each reactive power. AVAROS[23:0], BVAROS[23:0], and CVAROS[23:0] registers compensate the offsets in the total reactive power calculations. These are signed twos complement, 24-bit registers that are used to remove offsets in the reactive power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed. The offset registers' resolution is the same as the active power offset registers (see the Active Power Offset Calibration section). As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVAROS, BVAROS, CVAROS 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
calculate the total reactive power in the ADE7858 for each phase. The instantaneous reactive power signal q(t) is generated by multiplying each harmonic of the voltage signals by the 90 phase-shifted corresponding harmonic of the current in each phase. The ADE7858 stores the instantaneous total phase reactive powers into AVAR[23:0], BVAR[23:0] and CVAR[23:0] registers. Their expression is:
xVAR where: x=A, B, C UFS, IFS are the rms values of the phase voltage and current when the ADC inputs are at full scale. PMAX=33,516,139 is the instantaneous power computed when the ADC inputs are at full scale and in phase. The xVAR[23:0], x=A, B, C waveform registers may be accessed using various serial ports. Refer to Waveform Sampling Mode chapter for more details.
Uk
k 1 U FS
Ik I FS
sin k k PMAX
1 24
(32)
Sign of Reactive Power Calculation
Note that the reactive power is a signed calculation. Table 14 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. The ADE7858 has a sign detection circuitry for reactive power calculations. As will be seen in the Reactive Energy Calculation section, the reactive energy accumulation is executed in two stages. Every time a sign change is detected in the energy accumulation at the end of the first stage, that is after the energy accumulated into the 48 bit accumulator reaches VARTHR[47:0] threshold, a dedicated interrupt is triggered.
Reactive Power Gain Calibration
The average reactive power from the LPF output in each phase can be scaled by 100% by writing to the phase's VAR gain 24-bit register (AVARGAIN[23:0], BVARGAIN[23:0], CVARGAIN[23:0], AFVARGAIN[23:0], BFVARGAIN[23:0] or
Rev. PrA| Page 38 of 76
Preliminary Technical Data
The sign of each phase reactive power may be read in PHSIGN[15:0] register. Bits 12, 11, 10 (REVRPC, REVRPB and respectively REVRPA) in STATUS0[31:0] are set when a sign change occurs in the total reactive power. Bits 6, 5, 4 (CVARSIGN, BVARSIGN and respectively AVARSIGN) in PHSIGN[15:0] register are set simultaneously with REVRPC, REVRPB and REVRPA bits. They indicate the sign of the reactive power. When they are 0, the reactive power is positive. When they are 1, the reactive power is negative. Bit REVRPx of STATUS0[31:0] and bit xVARSIGN in PHSIGN[15:0] refers to the reactive power of phase x, x=A,B or C. Setting bits 12, 11, 10 in MASK0[31:0] register enables REVRPC, REVRPB and REVRPA interrupts respectively. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever a change of sign occurs. To find the phase that triggered the interrupt, PHSIGN[15:0] register is read immediately after reading STATUS0[31:0]. Then the status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1.
Table 14. Sign of Reactive Power Calculation
1 Between 0 to +90 Between -90 to 0 Between 0 to +90 Between -90 to 0
1
ADE7858
BVARHR[31:0] and CVARHR[31:0] represent the phase total reactive powers. Figure 42 from the Active Energy Calculation section explains this process. The VARTHR[47:0] 48-bit signed register contains the threshold and it is introduced by the user. Its value depends on how much energy is assigned to 1LSB of var-hour registers. Let's suppose a derivative of varh [10n varh], n an integer, is desired as 1LSB of VARHR. Then VARTHR may be computed using the following expression: VARTHR where: PMAX=33,516,139=0x1FF6A6B, the instantaneous power computed when the ADC inputs are at full scale. fs=8KHz is the frequency with which the DSP computes the instantaneous power. UFS, IFS are the rms values of phase voltages and currents when the ADC inputs are at full scale. The maximum value that may be written on VARTHR[47:0] is 247-1. The minimum value is 0x0, but it is recommended to write a number equal or greater than PMAX. Negative numbers should never be used. The VARTHR[47:0] is a 48-bit register. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the WTHR[47:0] register presented in Figure 43, VARTHR[47:0] is accessed as two 32-bit registers (VARTHR1[31:0] and VARTHR0[31:0]), each having 8 most significant bits padded with 0s. This discrete time accumulation or summation is equivalent to integration in continuous time following the description in expression (34).
Re activeEnergy q t dt Lim q nT T T0 n 0
(34)
PMAX f s 3600 10 n U FS I FS
Integrator Off Off On On
Sign of Reactive Power Positive Negative Positive Negative
is defined as the phase angle of the voltage signal minus the current signal; that is, is positive if the load is inductive and negative if the load is capacitive.
Reactive Energy Calculation
Reactive energy is defined as the integral of reactive power.
Reactive Energy qt dt
(34)
Total reactive energy accumulation is always a signed operation. Negative energy is subtracted from the reactive energy contents. Similar to active power, the ADE7858 achieves the integration of the reactive power signal in two stages (see Figure 45). The first stage is done inside the DSP: every 125sec (8KHz frequency), the instantaneous phase total reactive power is accumulated into an internal register. When a threshold is reached, a pulse is generated at processor port and the threshold is subtracted from the internal register. The sign of the energy in this moment is considered the sign of the reactive power (see Sign of Reactive Power Calculation section for details).The second stage is done outside the DSP and consists in accumulating the pulses generated by the processor into internal 32-bit accumulation registers. The content of these registers is transferred to var-hr registers xVARHR[31:0], x=A, B, C when these registers are accessed. AVARHR[31:0],
where:
n is the discrete time sample number. T is the sample period.
On the ADE7858, the total phase reactive powers are accumulated in AVARHR[31:0], BVARHR[31:0] and CVARHR[31:0] 32-bit signed registers. The reactive energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the reactive power is positive. Conversely, if the reactive power is negative, the energy register would underflow to full-scale positive (0x7FFFFFFF) and continue decreasing in value. Bit 2 (REHF) in STATUS0[31:0] register is set when bit 30 of one of xVARHR, x=A,B,C registers changes, signifying one of these registers is half full. If the reactive power is positive, the var-hr register becomes half full when it increments from
Rev. PrA | Page 39 of 76
ADE7858
0x3FFF FFFF to 0x4000 0000. If the reactive power is negative, the var-hr register becomes half full when it decrements from 0xC000 0000 to 0xBFFF FFFF. Setting bit 2 in MASK0[31:0] register enables the REHF interrupt. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever one of the energy registers xVARHR (for
AIGAIN HPFDIS[23:0] Digital Integrator
Preliminary Technical Data
REHF interrupt), x=A, B, C becomes half full. The status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1. Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a read-with-reset for all var-hr accumulation registers, that is, the registers are reset to 0 after a read operation.
iA AVAROS Total Reactive Power Algorithm AVARGAIN
REVRPA bit in STATUS0[31:0]
AVARHR[31:0]
APHCAL
HPFDIS[23:0] HPF
ACCUMULATOR
VARTHR[47:0]
32 bit register
vA
AVGAIN Digital Signal Processor
Figure 45. ADE7858 Total Reactive Energy Accumulation
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register is 125s (1/8KHz). With full-scale pure sinusoidal signals on the analog inputs, a 90 phase difference between the voltage and the current signal (the largest possible reactive power), the average word value representing the reactive power is PMAX=33,516,139=0x1FF6A6B. If the VARTHR[47:0] threshold is set at PMAX level, this means the DSP generates a pulse that is added at var-hr registers every 125 s. The maximum value that can be stored in the var-hr accumulation register before it overflows is 231 - 1 or 0x7FFFFFFF. The integration time is calculated as
total active powers. While the var-hr accumulation registers accumulate the reactive power in a signed format, the frequency output may be generated in signed mode or in sign adjusted mode, function of VARACC[1:0]. See Energy to Frequency Conversion chapter for details.
Line Cycle Reactive Energy Accumulation Mode
As mentioned in Line Cycle Active Energy Accumulation Mode section, in line cycle energy accumulation mode, the energy accumulation can be synchronized to the voltage channel zero crossings so that reactive energy can be accumulated over an integral number of half line cycles. In this mode, the ADE7858 transfers the reactive energy accumulated in the 32-bit internal accumulation registers into xVARHR[31:0], x=A,B,C registers after an integral number of line cycles, as shown in Figure 46. The number of half line cycles is specified in the LINECYC[15:0] register. The line cycle reactive energy accumulation mode is activated by setting bit 1 (LVAR) in the LCYCMODE[7:0] register. The total reactive energy accumulated over an integer number of ahlf line cycles or zero crossings is accumulated in the var-hr accumulation registers after the LINECYC number of zero crossings is detected. When using the line cycle accumulation mode, bit 6 (RSTREAD) of the LCYCMODE[7:0] register should be set to Logic 0 because the read with reset of var-hr registers is not available in this mode.
Time 0 x7FFF, FFFF 125s 74h33 min 55s
(35)
Energy Accumulation Modes
The reactive power accumulated in each var-hr accumulation 32-bit register (AVARHR, BVARHR, CVARHR) depends on the configuration of bits 5, 4 (CONSEL) in the ACCPMODE[7:0] register, in correlation with the watt-hr registers. The different configurations are described in Table 15. Note that IA'/IB'/IC' are the phase-shifted current waveforms.
Table 15. Inputs to VAR-Hr Accumulation Registers
CONSEL[1,0] 00 01 10 11 AVARHR, AFVARHR VA x IA' VA x IA' VA x IA' VA x IA' BVARHR, BFVARHR VB x IB' 0 VB x IB' VB=-VA-VC VB x IB' VB=-VA CVARHR, CFVARHR VC x IC' VC x IC' VC x IC' VC x IC'
Bits 3, 2 (VARACC[1:0]) in ACCMODE[7:0] register determine how CF frequency output may be generated function of the
Rev. PrA| Page 40 of 76
Preliminary Technical Data
ZXSEL[0] in LCYCMODE[7:0] ZERO CROSSING DETECTION (PHASE A) ZXSEL[1] in LCYCMODE[7:0] LINECYC[15:0]
ADE7858
where S is the apparent power and VRMS and IRMS are the rms voltage and current, respectively. It is also called the arithmetic apparent power. The ADE7858 computes the arithmetic apparent power on each phase. Figure 47 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7858. As VRMS and IRMS contain all harmonic information, the apparent power computed by the ADE7858 is a total apparent power.
AVARHR[31:0]
ZERO CROSSING DETECTION (PHASE B) ZXSEL[2] in LCYCMODE[7:0]
CALIBRATION CONTROL
ZERO CROSSING DETECTION (PHASE C)
AVAROS Output from Total Reactive Power Algorithm
AVARGAIN
ACCUMULATOR
VARHR[47:0]
32 bit register
The ADE7858 stores the instantaneous phase apparent powers into AVA[23:0], BVA[23:0] and CVA[23:0] registers. Their expression is: xVA where: x=A, B, C U, I are the rms values of the phase voltage and current. UFS, IFS are the rms values of the phase voltage and current when the ADC inputs are at full scale. PMAX=33,516,139 is the instantaneous power computed when the ADC inputs are at full scale and in phase. The xVA[23:0], x=A, B, C waveform registers may be accessed using various serial ports. Refer to Waveform Sampling Mode chapter for more details. The ADE7858 may compute the apparent power in an alternative way by multiplying the phase rms current by an rms voltage introduced externally. See Apparent Power Calculation using VNOM section for details. U I 1 PMAX 4 U FS I FS 2
(37)
Figure 46. ADE7858 Line Cycle Reactive Energy Accumulation Mode
Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting bits 5, 4, 3 (ZXSEL) in the LCYCMODE[7:0] register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration. For details on setting LINECYC[15:0] register and the interrupt LENERGY associated with the line cycle accumulation mode, see Line Cycle Active Energy Accumulation Mode section.
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be delivered to a load. One way to obtain the apparent power is by multiplying the voltage rms value by the current rms value:
S VRMS IRMS
(36)
AIRMS
AVAGAIN AVAHR[31:0]
ACCUMULATOR
AVRMS Digital Signal Processor
Figure 47. Apparent Power data flow and Apparent Energy Accumulation
32 bit register
VATHR[47:0]
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled by 100% by writing to the phase's VAGAIN 24-bit register (AVAGAIN[23:0], BVAGAIN[23:0] or CVAG AIN[23:0]). The VAGAIN registers are twos complement, signed registers and
have a resolution of 2-23/LSB. The function of the VA gain registers is expressed mathematically as
Rev. PrA | Page 41 of 76
ADE7858
Average Apparent Power VAGAIN Register VRMS IRMS 1 2 23
(38)
Preliminary Technical Data
Similar to active and reactive powers, the ADE7858 achieves the integration of the apparent power signal in two stages (see Figure 47). The first stage is done inside the DSP: every 125sec (8KHz frequency), the instantaneous phase apparent power is accumulated into an internal register. When a threshold is reached, a pulse is generated at processor port and the threshold is subtracted from the internal register. The second stage is done outside the DSP and consists in accumulating the pulses generated by the processor into internal 32-bit accumulation registers. The content of these registers is transferred to va-hr registers xVAHR[31:0], x=A, B, C when these registers are accessed. Figure 42 from the Active Energy Calculation section explains this process. The VATHR[47:0] 48-bit register contains the threshold. Its value depends on how much energy is assigned to 1LSB of VA-hour registers. Let's suppose a derivative of VAh [10n VAh], n an integer, is desired as 1LSB of VAHR. Then VATHR may be computed using the following expression: VATHR where: PMAX=33,516,139=0x1FF6A6B, the instantaneous power computed when the ADC inputs are at full scale. fs=8KHz is the frequency with which the DSP computes the instantaneous power. UFS, IFS are the rms values of phase voltages and currents when the ADC inputs are at full scale. The VATHR[47:0] is a 48-bit register. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the WTHR[47:0] register presented in Figure 43, VATHR[47:0] is accessed as two 32-bit registers (VATHR1[31:0] and VATHR0[31:0]), each having 8 most significant bits padded with 0s. This discrete time accumulation or summation is equivalent to integration in continuous time following the description in expression (41).
ApparentEnergy s t dt Lim s nT T T 0 n 0
(41)
The output is scaled by -50% by writing 0xC00000 to the VA gain registers and increased by +50% by writing 0x400000 to them. These registers can be used to calibrate the apparent power (or energy) calculation in the ADE7858 for each phase. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVAGAIN, BVAGAIN, CVAGAIN 24-bit registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Root Mean Square Measurement section). The voltage and current rms values are then multiplied together in the apparent power signal processing. As no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement.
PMAX f s 3600 10 n U FS I FS
Apparent Power Calculation using VNOM
The ADE7858 may compute the apparent power multiplying the phase rms current by an rms voltage introduced externally in VNOM[23:0] 24-bit signed register. When one of bits 13, 12, 11 (VNOMCEN, VNOMBEN, VNOMAEN) in COMPMODE[15:0] register is set to 1, the apparent power in the corresponding phase (phase x for VNOMxEN, x=A,B,C) is computed in this way. When bits VNOMxEN are cleared to 0, the default value, then the arithmetic apparent power is computed. VNOM[23:0] register contains a number determined by U, the desired rms voltage and U FS , the rms value of the phase voltage when the ADC inputs are at full scale: U VNOM 4,191,400 U FS Usually U is the nominal phase rms voltage. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. Similar to the register presented in Figure 16, VNOM 24-bit signed register is accessed as a 32-bit register with 8 most significant bits padded with 0s.
(39)
where:
n is the discrete time sample number. T is the sample period.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
ApparentEnergy s (t )dt
(40)
In the ADE7858, the phase apparent powers are accumulated in AVAHR[31:0], BVAHR[31:0] and CVAHR[31:0] 32-bit signed registers. The apparent energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the apparent power is positive. Conversely, if because of offset compensation in rms data path, the apparent power is negative, the energy register would underflow to fullscale positive (0x7FFFFFFF) and continue decreasing in value.
Rev. PrA| Page 42 of 76
Preliminary Technical Data
Bit 4 (VAEHF) in STATUS0[31:0] register is set when bit 30 of one of xVAHR, x=A, B, C registers changes, signifying one of these registers is half full. As the apparent power is always positive and xVAHR, x=A, B, C registers are signed, the VA-hr registers become half full when they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts attached to bit VAEHF in STATUS0[31:0] register may be enabled by setting bit 4 in MASK0[31:0] register. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever one of the energy registers xVAHR, x=A, B, C becomes half full. The status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1. Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a read-with-reset for all va-hr accumulation registers, that is, the registers are reset to 0 after a read operation.
ADE7858
accumulation registers into xVAHR[31:0], x=A,B,C registers after an integral number of line cycles, as shown in Figure 48. The number of half line cycles is specified in the LINECYC[15:0] register. The line cycle apparent energy accumulation mode is activated by setting bit 2 (LVA) in the LCYCMODE[7:0] register. The apparent energy accumulated over an integer number of zero crossings is written to the VA-hr accumulation registers after the LINECYC number of zero crossings is detected. When using the line cycle accumulation mode, bit 6 (RSTREAD) of the LCYCMODE[7:0] register should be set to Logic 0 because the read with reset of VA-hr registers is not available in this mode.
ZXSEL[0] in LCYCMODE[7:0]
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register is 125s (1/8 KHz). With full-scale pure sinusoidal signals on the analog inputs, the average word value representing the apparent power is PMAX. If the VATHR threshold is set at PMAX level, this means the DSP generates a pulse that is added at VA-hr registers every 125 s. The maximum value that can be stored in the va-hr accumulation register before it overflows is 231 - 1 or 0x7FFFFFFF. The integration time is calculated as
ZERO CROSSING DETECTION (PHASE A) ZXSEL[1] in LCYCMODE[7:0] LINECYC[15:0]
ZERO CROSSING DETECTION (PHASE B) ZXSEL[2] in LCYCMODE[7:0]
CALIBRATION CONTROL
ZERO CROSSING DETECTION (PHASE C)
AIRMS
AVAGAIN AVAHR[31:0]
ACCUMULATOR
Time 0 x7FFF, FFFF 125s 74h33 min 55s
(42)
AVRMS VAHR[47:0]
32 bit register
Energy Accumulation Mode
The apparent power accumulated in each VA-hr accumulation register (AVAHR[31:0], BVAHR[31:0] or CVAHR[31:0]) depends on the configuration of bits 5,4 (CONSEL) in the ACCMODE[7:0] register. The different configurations are described in Table 16.
Table 16. Inputs to VA-Hr Accumulation Registers
CONSEL[1,0] 00 01 10 AVAHR AVRMS x AIRMS AVRMS x AIRMS AVRMS x AIRMS AVRMS x AIRMS BVAHR BVRMS x BIRMS 0 BVRMS x BIRMS VB=-VA-VC BVRMS x BIRMS VB=-VA CVAHR CVRMS x CIRMS CVRMS x CIRMS CVRMS x CIRMS CVRMS x CIRMS
Figure 48. ADE7858 Line Cycle Apparent Energy Accumulation Mode
Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting bits 5,4,3 (ZXSEL) in the LCYCMODE[7:0] register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration. For details on setting LINECYC[15:0] register and the interrupt LENERGY associated with the line cycle accumulation mode, see Line Cycle Active Energy Accumulation Mode section.
WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform, the active, reactive, and apparent power multiplier outputs are stored every 125sec (8KHz rate) into 24-bit signed registers that may be accessed through various serial ports of the ADE7858. Table 17 presents the list of the registers and their description.
Table 17. Waveform registers list
Register IAWV VAWV Description Phase A current Phase A voltage Register CVA AWATT Description Phase C apparent power Phase A active
11
Line Cycle Apparent Energy Accumulation Mode
As mentioned in Line Cycle Active Energy Accumulation Mode section, in line cycle energy accumulation mode, the energy accumulation can be synchronized to the voltage channel zero crossings so that apparent energy can be accumulated over an integral number of half line cycles. In this mode, the ADE7858 transfers the apparent energy accumulated in the 32-bit internal
Rev. PrA | Page 43 of 76
ADE7858
Register IBWV VBWV ICWV VCWV AVA BVA Description Phase B current Phase B voltage Phase C current Phase C voltage Phase A apparent power Phase B apparent power Register BWATT CWATT AVAR BVAR CVAR Description power Phase B active power Phase C active power Phase A reactive power Phase B reactive power Phase C reactive power
Preliminary Technical Data
waveform sample registers. Read HSDC Interface section for more details. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words. All registers listed in Table 17 are transmitted signed extended from 24 to 32 bits (see Figure 18).
ENERGY TO FREQUENCY CONVERSION
The ADE7858 provides 3 frequency output pins: CF1, CF2 and CF3. CF3 pin is multiplexed with HSCLK pin of HSDC interface. When HSDC is enabled, the CF3 functionality is disabled at the pin. CF1 and CF2 pins are always available. After initial calibration at manufacturing, the manufacturer or end customer verifies the energy meter calibration. One convenient way to verify the meter calibration is to provide an output frequency proportional to the active, reactive or apparent powers under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 49 illustrates the energyto-frequency conversion in the ADE7858.
The bit 17 (DREADY) in STATUS0[31:0] register can be used to signal when the registers mentioned in Table 17 may be read using I2C or SPI serial ports. An interrupt attached to the flag may be enabled by setting bit 17 (DREADY) in MASK0[31:0] register. See Digital Signal Processor chapter for more details on bit DREADY. The ADE7858 contains a High Speed Data Capture (HSDC) port that is specially designed to provide fast access to the
CFxSEL bits in CFMODE Instantaneous phase A active power TERMSELx bits in COMPMODE Instantaneous phase B active power VA WATT VAR 27
x
REVPSUMx bit of STATUS0[31:0] ACCUMULATOR Freq Divider WTHR[47:0] CFx pulse output
Instantaneous phase C active power
x
CFxDEN 27
Digital Signal Processor
Figure 49. ADE7858 Energy to Frequency Conversion
The DSP computes the instantaneous values of all phase powers: total active, total reactive and apparent. The process in which the energy is sign accumulated in various hr registers (watt-hr, var-hr and VA-hr) has already been described in Energy Calculation chapters. In the energy to frequency conversion process, the instantaneous powers are used to generate signals at frequency output pins CF1, CF2 and CF3. One digital to frequency converter is used for every CF pin. Every converter sums certain phase powers and generates a signal proportional to the sum. Two sets of bits decide what powers are converted. First, bits 2, 1, 0 (TERMSEL1[2:0]), 5, 4, 3 (TERMSEL2[2:0]) and 8, 7, 6 (TERMSEL3[2:0]) of COMPMODE[15:0] register decide which phases or which combination of phases are added. TERMSEL1 bits refer to CF1 pin, TERMSEL2 bits refer to CF2 pin and TERMSEL3 bits refer to CF3 pin. TERMSELx[0] bits,
x=1, 2, 3 manage phase A. When set to 1, phase A power is included in the sum of powers at CFx converter. When cleared to 0, phase A power is not included. TERMSELx[1] bits manage phase B, TERMSELx[2] bits manage phase C. Setting all TERMSELx bits to 1 means all 3 phase powers are added at CFx converter. Clearing all TERMSELx bits to 0 means no phase power is added and no CF pulse is generated. Second, bits 2, 1, 0 (CF1SEL[2:0]), 5, 4, 3 (CF2SEL[2:0]) and 8, 7, 6 (CF3SEL[2:0]) in CFMODE[15:0] register decide what type power is used at the inputs of CF1, CF2 and respective CF3 converters. Table 18 shows the values that CFxSEL may have: total active, total reactive or apparent powers. By default, TERMSELx bits are all 1 and CF1SEL bits are 000, CF2SEL bits are 001 and CF3SEL bits are 010. This means that by default, the CF1 digital to frequency converter produces signals proportional to the sum of all 3 phase total active
Rev. PrA| Page 44 of 76
Preliminary Technical Data
powers, CF2 produces signals proportional to total reactive powers and CF3 produces signals proportional to apparent
Table 18. CFxSEL, x=1,2,3 bits description
CFxSEL 000 001 010 011 to 111 Description CFx signal proportional to the sum of total phase active powers CFx signal proportional to the sum of total phase reactive powers CFx signal proportional to the sum of phase apparent powers Reserved
ADE7858
powers.
Registers latched when CFxLATCH=1 AWATTHR, BWATTHR, CWATTHR AVARHR, BVARHR, CVARHR AVAHR, BVAHR, CVAHR
Similar to the energy accumulation process, the energy to frequency conversion is done in two stages. In the first stage, the instantaneous phase powers obtained from the DSP at 8KHz rate are shifted left 7 bits and then accumulated into an internal register at 1MHz rate. When a threshold is reached, a pulse is generated and the threshold is subtracted from the internal register. The sign of the energy in this moment is considered the sign of the sum of phase powers (see Sign of sum of phase powers in CFx data path section for details). The threshold is the same threshold used in various active, reactive and appearent energy accumulators in DSP, WTHR[47:0], VARTHR[47:0] or VATHR[47:0], but this time it is shifted left 7 bits. The advantage of accumulating the instantaneous powers at 1MHz rate is that the ripple at CFx pins is greatly diminished. The second stage consists in a frequency divider by CFxDEN[15:0], x=1, 2, 3, 16-bit unsigned registers. The values of CFxDEN depend on the meter constant (MC), measured in impulses/kwh and how much energy is assigned to 1LSB of various energy registers: WATT-hr, VAR-hr, etc. Let's suppose a derivative of wh, [10n wh], n a positive or negative integer, is desired as 1LSB of WATTHR. Then CFxDEN is: CFxDEN 10 3 MC[imp / kwh] 10 n
(43)
and the pin stays high. When bit CFxDIS is cleared to 0, the correspondent CFx pin output generates an active low signal. Bits 16, 15, 14 (CF3, CF2, CF1) in interrupt mask register MASK0[31:0] manage CF3, CF2 and CF1 related interrupts. When CFx, x=1, 2, 3 bits are set, whenever a high to low transition at corresponding frequency converter output occurs, an interrupt IRQ0 is triggered and a status bit in STATUS0[31:0] register is set to 1. The interrupt is available even if the CFx output is not enabled by CFxDIS bits in CFMODE[15:0].
VDD
CFx pin
The derivative of wh must be chosen in such a way to obtain a CFxDEN greater than 1. If CFxDEN=1, then the CF stays active low for only 1sec, so this number should be avoided. Fractional results cannot be accommodated by the frequency converter, so the result of the division has to be rounded to the nearest integer. If CFxDEN is set equal to 0, then the ADE7858 considers it as equal to 1. The pulse output for all digital to frequency converters stays low for 80ms if the pulse period is larger than 160ms (6.25Hz). If the pulse period is smaller than 160ms and CFxDEN is an even number, the duty cycle of the pulse output is exactly 50%. If the pulse period is smaller than 160ms and CFxDEN is an odd number, the duty cycle of the pulse output is 1 1 CFDEN 50% . The pulse output is active low and should be preferably connected to an LED as shown in Figure 50. Bits 11, 10, 9 (CF3DIS , CF2DIS and CF1DIS) of CFMODE[15:0] register decide if the frequency converter output is generated at CF3, CF2 or CF1 pins. When bit CFxDIS, x=1, 2, 3 is set to 1, the default value, the CFx pin is disabled
Figure 50. CF pin recommended connection
Synchronizing energy registers with CFx outputs
The ADE7858 contains a feature that allows synchronizing the content of phase energy accumulation registers with the generation of a CFx pulse. When a high to low transition at one frequency converter output occurs, the content of all internal phase energy registers that relate to the power being output at CFx pin is latched into hr registers and then is reset to 0. See Table 18 for the list of registers that are latched based on CFxSEL[2:0] bits in CFMODE[15:0] register. All 3 phase registers are latched independent of TERMSELx bits of COMPMODE[15:0] register. The process is shown in Figure 51 for CF1SEL[2:0]=010 (apparent powers contribute at CF1 pin) and CFCYC=2. CFCYC[7:0] 8-bit unsigned register contains the number of high to low transitions at frequency converter output between two consecutive latches. Writing a new value into CFCYC[7:0] register during a high to low transition at any CFx pin should be avoided.
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ADE7858
CF1 pulse based on phase A and phase B apparent powers CFCYC=2 AVAHR, BVAHR, CVAHR latched Energy registers reset
Preliminary Technical Data
reactive powers are chosen at CFx pins (bits CFxSEL[2:0], x=1, 2, 3 in CFMODE[15:0] register are equal to 001 or to 100). When VARACC[1:0]=00, the default value, the reactive powers are sign accumulated before entering the energy to frequency converter. Figure 54 presents the way signed reactive power accumulation works. Note that in this mode, the CF pulses are perfectly synchronized with the reactive energy accumulated in var-hr registers because the powers are sign accumulated in both data paths.
AVAHR, BVAHR, CVAHR latched Energy registers reset
Figure 51.Synchronizing AVAHR and BVAHR with CF1
Bits 14, 13, 12 (CF3LATCH, CF2LATCH and CF1LATCH) of CFMODE[15:0] register enable this process when set to 1. When cleared to 0, the default state, no latch occurs. The process is available even if the CFx output is not enabled by CFxDIS bits in CFMODE[15:0].
CF outputs for various accumulation modes
The bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register determine the accumulation modes of the total active powers when signals proportional to the active powers are chosen at CFx pins (bits CFxSEL[2:0], x=1,2,3 in CFMODE[15:0] register are equal to 000). When WATTACC[1:0]=00, the default value, the active powers are sign accumulated before entering the energy to frequency converter. Figure 52 presents the way signed active power accumulation works. Note that in this mode, the CF pulses are perfectly synchronized with the active energy accumulated in watt-hr registers because the powers are sign accumulated in both data paths.
ACTIVE ENERGY
NO-LOAD THRESHOLD
ACTIVE POWER
NO-LOAD THRESHOLD
ACTIVE ENERGY
REVAPx bit in STATUS0 xWSIGN bit in PHSIGN
NO-LOAD THRESHOLD
APNOLOAD SIGN=POSITIVE
POS
NEG
POS
NEG
Figure 53. Active power absolute accumulation mode
ACTIVE POWER
NO-LOAD THRESHOLD REVAPx bit in STATUS0 xWSIGN bit in PHSIGN APNOLOAD SIGN=POSITIVE POS NEG POS NEG
REACTIVE ENERGY
NO-LOAD THRESHOLD
Figure 52. Active power signed accumulation mode
REACTIVE POWER
When WATTACC[1:0]=11, the active powers are accumulated in absolute mode. When the powers are negative, they change sign and are accumulated together with the positive power. Figure 53 presents the way absolute active power accumulation works. Note that in this mode, the watt-hr registers continue to accumulate active powers in signed mode, even if the CF pulses are generated based on the absolute accumulation mode. The bits 3, 2 (VARACC[1:0]) in ACCMODE[7:0] register determine the accumulation modes of the total and fundamental reactive powers when signals proportional to the
NO-LOAD THRESHOLD REVRPx bit in STATUS0 xVARSIGN bit in PHSIGN VARNOLOAD SIGN=POSITIVE POS NEG POS NEG
Figure 54. Reactive power signed accumulation mode
Rev. PrA| Page 46 of 76
Preliminary Technical Data
When VARACC[1:0]=10, the reactive powers are accumulated depending on the sign of corresponding active power. If the active power is positive, the reactive power is accumulated as is. If the active power is negative, the sign of the reactive power is changed for accumulation. Figure 55 presents the way the sign adjusted reactive power accumulation mode works. Note that in this mode, the var-hr registers continue to accumulate reactive powers in signed mode, even if the CF pulses are generated based on the sign adjusted accumulation mode.
ADE7858
change of the sum of powers in CF3, CF2 or CF1 data paths occurs. To correlate these events with the pulses generated at CFx pins, after a sign change occurs, bits REVPSUM3, REVPSUM2 and REVPSUM1 are set in the same moment in which a high to low transition at CF3, CF2 and respectively CF1 pin occurs. Bits 8, 7, 3 (SUM3SIGN, SUM2SIGN and respectively SUM1SIGN) of PHSIGN[15:0] register are set in the same moment with bits REVPSUM3, REVPSUM2 and REVPSUM1 and indicate the sign of the sum of phase powers. When cleared to 0, the sum is positive. When set to 1, the sum is negative. Interrupts attached to the bits 18, 13, 9 (REVPSUM3, REVPSUM2, and respectively REVPSUM1) in STATUS0[31:0] register may be enabled by setting bits 18, 13 , 9 in MASK0[31:0] register. If enabled, the IRQ0 pin is set low and the status bit is set to 1 whenever a change of sign occurs. To find the phase that triggered the interrupt, PHSIGN[15:0] register is read immediately after reading STATUS0[31:0]. Then the status bit is cleared and IRQ0 pin is set back high by writing STATUS0 register with the corresponding bit set to 1.
REACTIVE ENERGY
NO-LOAD THRESHOLD
REACTIVE POWER
NO-LOAD CONDITION
NO-LOAD THRESHOLD
NO-LOAD THRESHOLD
The no-load condition is defined in metering equipment standards as occurring when the voltage is applied to the meter and no current flows in the current circuit. To eliminate any creep effects in the meter, the ADE7858 contains two separate no-load detection circuits: one related to the total active and reactive powers and one related to the apparent powers.
ACTIVE POWER
No-load detection based on total active and reactive powers
This no-load condition is triggered when the absolute values of both phase total active and reactive powers are less than or equal to positive thresholds indicated in APNOLOAD[23:0] and respective VARNOLOAD[23:0] signed 24-bit registers. In this case, the total active and reactive energies of that phase are not accumulated and no CF pulses are generated based on these energies. APNOLOAD[23:0] represents the positive no-load level of active power relative to PMAX, the maximum active power obtained when full scale voltages and currents are provided at ADC inputs. VARNOLOAD[23:0] represents the positive no-load level of reactive power relative to PMAX. The expression used to compute APNOLOAD[23:0] signed 24-bit value is:
APNOLOAD U n I noload PMAX U FS I FS
(44)
NO-LOAD THRESHOLD REVRPx bit in STATUS0 xVARSIGN bit in PHSIGN VARNOLOAD SIGN=POSITIVE POS NEG POS
Figure 55. Reactive power accumulation in sign adjusted mode
Sign of sum of phase powers in CFx data path
The ADE7858 has a sign detection circuitry for the sum of phase powers that are used in CFx, x=1, 2, 3 data path. As seen in the beginning of Energy to Frequency Conversion chapter, the energy accumulation in CFx data path is executed in two stages. Every time a sign change is detected in the energy accumulation at the end of the first stage, that is after the energy accumulated into the 55 bit accumulator reaches one of WTHR[47:0], VARTHR[47:0 or VATHR[47:0] thresholds, a dedicated interrupt may be triggered synchronously with the corresponding CF pulse. The sign of each sum may be read in PHSIGN[15:0] register. Bits 18, 13, 9 (REVPSUM3, REVPSUM2, and respectively REVPSUM1) of STATUS0[31:0] register are set to 1 when a sign
where: PMAX=33,516,139=0x1FF6A6B, the instantaneous power computed when the ADC inputs are at full scale UFS, IFS, the rms values of phase voltages and currents when the ADC inputs are at full scale. Un, the nominal rms value of phase voltage.
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ADE7858
Inoload, the minimum rms value of phase current the meter starts measuring. VARNOLOAD[23:0] contains usually the same value as APNOLOAD[23:0]. When APNOLOAD and VARNOLOAD are set to negative values, the no-load detection circuit is disabled. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. APNOLOAD and VARNOLOAD 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits. See Figure 15 for details. Bit 0 (NLOAD) in STATUS1[31:0] register is set when this noload condition in one of the three phases is triggered. Bits 2, 1, 0 (NLPHASE[2:0]) in PHNOLOAD[15:0] register indicate the state of all phases relative to no-load condition and are set simultaneously with bit NLOAD in STATUS1[31:0]. NLPHASE[0] indicates the state of phase A , NLPHASE[1] the state of phase B, NLPHASE[2] the state of phase C. When bit NLPHASE[x], x=0, 1, 2 is cleared to 0, it means the phase is out of no-load condition. When set to 1, it means the phase is in no-load condition. An interrupt attached to the bit 0 (NLOAD) in STATUS1[31:0] may be enabled by setting bit 0 in MASK1[31:0] register. If enabled, the IRQ1 pin is set low and the status bit is set to 1 whenever one of three phases enters or exits this no-load condition. To find the phase that triggered the interrupt, PHNOLOAD[15:0] register is read immediately after reading STATUS1[31:0]. Then the status bit is cleared and IRQ1 pin is set back high by writing STATUS1 register with the corresponding bit set to 1.
Preliminary Technical Data
When VANOLOAD[23:0] is set to negative values, the no load detection circuit is disabled. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented inFigure 15, VANOLOAD 24-bit signed register is accessed as a 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits. Bit 2 (VANLOAD) in STATUS1[31:0] register is set when this no-load condition in one of the three phases is triggered. Bits 8, 7, 6 (VANLPHASE[2:0]) in PHNOLOAD[15:0] register indicate the state of all phases relative to no-load condition and are set simultaneously with bit VANLOAD in STATUS1[31:0]. VANLPHASE[0] indicates the state of phase A , VANLPHASE[1] the state of phase B, VANLPHASE[2] the state of phase C. When bit VANLPHASE[x], x=0, 1, 2 is cleared to 0, it means the phase is out of no-load condition. When set to 1, it means the phase is in no-load condition. An interrupt attached to the bit 2 (VANLOAD) in STATUS1[31:0] may be enabled by setting bit 2 in MASK1[31:0] register. If enabled, the IRQ1 pin is set low and the status bit is set to 1 whenever one of three phases enters or exits this no-load condition. To find the phase that triggered the interrupt, PHNOLOAD[15:0] register is read immediately after reading STATUS1[31:0]. Then the status bit is cleared and IRQ1 pin is set back high by writing STATUS1 register with the corresponding bit set to 1.
CHECKSUM REGISTER
The ADE7858 has a checksum 32-bit register CHECKSUM[31:0] that ensures certain very important configuration registers maintain their desired value during normal power mode PSM0. The registers covered by this register are MASK0[31:0], MASK1[31:0], COMPMODE[15:0], GAIN[15:0], CFMODE[15:0], CF1DEN[15:0], CF2DEN[15:0], CF3DEN[15:0], CONFIG[15:0], MMODE[7:0], ACCMODE[7:0], LCYCMODE[7:0], HSDC_CFG[7:0] and other six 8-bit reserved internal registers that always have default values. The ADE7858 computes the cyclic redundancy check (CRC) based on the IEEE802.3 standard. The registers are introduced one by one into a linear feedback shift register (LFSR) based generator starting with the less significant bit (as presented in Figure 56). The 32-bit result is written in CHECKSUM[31:0] register. After power up or a hardware/software reset, the CRC is computed on the default values of the registers. The result is 0x93D774E6. Figure 57 presents how LFSR works. Bits a0, a1,..., a255 represent the bits from the list of registers presented above. a0 is the less significant bit of the first internal register to enter LFSR, a255 is the most significant bit of MASK0[31:0] register, the last register to enter LFSR. The equations that govern LFSR are presented below:
No-load detection based on apparent power
This no-load condition is triggered when the absolute value of phase apparent power is less than or equal to the threshold indicated in VANOLOAD[23:0] 24-bit signed register. In this case, the apparent energy of that phase is not accumulated and no CF pulses are generated based on this energy. VANOLOAD represents the positive no-load level of apparent power relative to PMAX, the maximum apparent power obtained when full scale voltages and currents are provided at ADC inputs. The expression used to compute VANOLOAD[23:0] signed 24-bit value is: VANOLOAD U n I noload PMAX U FS I FS
where: PMAX=33,516,139=0x1FF6A6B, the instantaneous apparent power computed when the ADC inputs are at full scale UFS, IFS, the rms values of phase voltages and currents when the ADC inputs are at full scale. Un, the nominal rms value of phase voltage. Inoload, the minimum rms value of phase current the meter starts measuring.
Rev. PrA| Page 48 of 76
Preliminary Technical Data
bi(0) =1, i=0, 1, 2,..., 31, the initial state of the bits that form the CRC. b0 is the less significant bit, b31 is the most significant. gi, i=0,1,2,...,31 are the coefficients of the generating polynomial defined by IEEE802.3 standard: G(x) x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 g 0 g1 g 2 g 4 g 5 g 7 1 g 8 g 10 g 11 g 12 g 16 g 22 g 26 1 All the other gi coefficients are equal to 0.
(46) (45)
ADE7858
The operations and represent the logic XOR and AND. The equations (47), (48) and (49) have to be repeated for j=1, 2,..., 256. The value written into CHECKSUM[31:0] register contains the bits bi(256),i=0,1,...,31. The value of the CRC after the bits from the reserved internal register have passed through LFSR is 0x23F7C7B1. It is obtained at step j=48. Two different approaches may be followed in using the CHECKSUM register. One is to compute the CRC based on the relations (45) - (49) and then compare the value against the CHECKSUM register. Another is to periodically read the CHECKSUM[31:0] register. If two consecutive readings differ, then it may be safely assumed that one of the registers has changed value and therefore, the ADE7858 has changed configuration. The recommended response is to initiate a hardware/software reset that sets the values of all registers to the default, including the reserved ones, and then reinitialize the configuration registers.
+ LFSR generator
FB( j) a j1 b 31 ( j 1)
b 0 ( j) FB( j) g 0 b i ( j) FB( j) g i b i 1 ( j 1), i 1,2,3,...,31
31 0 31 MASK1 MASK0 255 248 0 15 0 15 COMPMODE GAIN 232 0 15 CFMODE 224 216 0
(47) (48) (49)
7
240
07 07 07 07 07 0 internal reg internal reg internal reg internal reg internal reg internal reg 40 32 24 87 0 16
Figure 56. CHECKSUM[31:0] register calculation
g0 b0 LFSR
g1 + b1
g2 + b2
g3 +
g31 + b31 +
FB
a255,a254,...,a2,a1,a0
Figure 57.LFSR generator used in CHECKSUM[31:0] register calculation
INTERRUPTS
The ADE7858 has two interrupt pins, IRQ0 and IRQ1 . Each of them is managed by a 32-bit interrupt mask register, MASK0[31:0], respective MASK1[31:0]. To enable an interrupt, a bit in MASKx[31:0] register has to be set to 1. To disable it, the bit has to be cleared to 0. Two 32-bit status registers, STATUS0[31:0] and STATUS1[31:0] are associated with the interrupts. When an interrupt event occurs in the ADE7858, the corresponding flag in the interrupt status register is set to a Logic 1 (see Table 28 and Table 29). If the mask bit for this interrupt in the interrupt mask register is Logic 1, then the IRQx logic output goes active low. The flag bits in the interrupt status register are set irrespective of the state of the mask bits.
To determine the source of the interrupt, the MCU should perform a read of corresponding STATUSx register and identify which bit is 1. To erase the flag in the status register, STATUSx should be written back with the flag set to 1. Practically, after an interrupt pin goes low, the status register is read and the source of the interrupt is identified. Then, the status register is written back without any change to cancel the status flag. The IRQx pin remains low until the status flag is cancelled. By default, all interrupts are disabled. RSTDONE interrupt is an exception. This interrupt can never be masked (disabled) and therefore bit 15 (RSTDONE) in MASK1[31:0] register does not have any functionality. IRQ1 pin always goes low and bit 15 (RSTDONE) in STATUS1[31:0] is set to 1 whenever a power up or a hardware/software reset process ends. To cancel the status
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ADE7858
flag, STATUS1[31:0] register has to be written with bit 15(RSTDONE) set to 1. Certain interrupts are used in conjunction with other status registers: bits 0 (NLOAD) and 2 (VANLOAD) in MASK1[31:0] work in conjunction with status bits in PHNOLAD[15:0]. Bits 16, (SAG), 17 (OI) and 18 (OV) in MASK1[31:0] work with status bits in PHSTATUS[15:0]. Bits 23 (PKI) and 24 (PKV) in MASK1[31:0] work with status bits in IPEAK[31:0] and respectively, VPEAK[31:0]. Bits 6, 7, 8 (REVAPx, x=A, B, C), 10, 11, 12 (REVRPx) and 9, 13, 18 (REVPSUMx) in MASK0[31:0] work with status bits in PHSIGN[15:0]. When STATUSx[31:0] register is read and one of these bits is set to 1, the status register associated with the bit is immediately read to identify the phase that triggered the interrupt and only now STATUSx[31:0] is written back with the bit set to 1.
Preliminary Technical Data
bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from STATUSx, the interrupt status register is carried out. The interrupt status register content is used to determine the source of the interrupt(s) and hence the appropriate action to be taken. Then, the same STATUSx content is written back into the ADE7858 to clear the status flag(s) and reset IRQx line to logic high (t2). If a subsequent interrupt event occurs during the ISR (t3) that event is recorded by the MCU external interrupt flag being set again. On returning from the ISR, the global interrupt mask bit is cleared (same instruction cycle) and the external interrupt flag uses the MCU to jump to its ISR once again. This ensures that the MCU does not miss any external interrupts. Figure 59 shows a recommended timing diagram when status bits in STATUSx registers work in conjunction with bits in other registers. Same as above, when IRQx pin goes active low, STATUSx register is read and if one of these bits is 1, then a second status register is read immediately to identify the phase that triggered the interrupt. The name PHx in the figure denotes one of PHSTATUS, IPEAK, VPEAK or PHSIGN registers. Then STATUSx is written back to clear the status flag(s).
MCU INTERRUPT FLAG SET
Using the Interrupts with an MCU
Figure 58 shows a timing diagram that illustrates a suggested implementation of the ADE7858 interrupt management using an MCU. At time t1, IRQx pin goes active low indicating that one or more interrupt events have occurred in the ADE7858. The IRQx pin should be tied to a negative-edge-triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled using the global interrupt mask
t1 t2
t3
IRQx
PROGRAM SEQUENCE JUMP to ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx WRITE BACK STATUSx ISR RETURN ISR ACTION GLOBAL INTERRUPT (BASED ON STATUSx CONTENTS) MASK RESET JUMP to ISR
Figure 58. ADE7858 interrupt management
t2 MCU INTERRUPT FLAG SET
t1
t3
IRQx
PROGRAM SEQUENCE JUMP to ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx READ PHx WRITE BACK STATUSx ISR RETURN ISR ACTION GLOBAL INTERRUPT (BASED ON STATUSx CONTENTS) MASK RESET JUMP to ISR
Figure 59. ADE7858 interrupt management when PHSTATUS, IPEAK, VPEAK or PHSIGN registers are involved
SERIAL INTERFACES
The ADE7858 has three serial port interfaces: one fully licensed I2C interface, one Serial Peripheral Interface (SPI) and one High Speed Data Capture Port (HSDC). As the SPI pins are multiplexed with some of the pins of I2C and HSDC ports, the ADE7858 accepts two configurations: one using SPI port only and one using I2C port in conjunction with HSDC port.
Serial interface choice
After reset, the HSDC port is always disabled. The choice between I2C and SPI port is done by manipulating the SS pin after power up or after a hardware reset. If SS pin is kept high, then the ADE7858 will use the I2C port until a new hardware reset is executed. If SS pin is toggled high low 3 times after power up or after a hardware reset, then the ADE7858 will use the SPI port until a new hardware reset is executed. This manipulation of the SS pin can be accomplished in two ways:
Rev. PrA| Page 50 of 76
Preliminary Technical Data
one way is to use the SS pin of the master device (i.e. the microcontroller) as a regular I/O pin and toggle it 3 times. Another way is to execute 3 SPI write operations to a location in the address space that is not allocated to a specific ADE7858 register (for example 0xEBFF, where 8 bit writes can be executed). These writes allow the SS pin to toggle 3 times. See SPI Write Operation section for details on the write protocol involved. After the serial port choice is done, it needs to be locked, so the active port remains in use until a hardware reset is executed in PSM0 normal mode or until a power down. If I2C is the active serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to 1 to lock it in. From this moment on, the ADE7858 ignores spurious togglings of the SS pin and an eventual switch into using SPI port is no longer possible. If SPI is the active serial port, any write to CONFIG2[7:0] register locks the port. From this moment on, a switch into using I2C port is no longer possible. Once locked, the serial port choice is maintained when the ADE7858 changes PSMx, x=0, 1, 2, 3 power modes. The functionality of the ADE7858 is accessible via several onchip registers. The contents of these registers can be updated or read using the I2C or SPI interfaces. HSDC port provides the state of up to 15 registers representing instantaneous values of phase voltages and currents, active, reactive and apparent powers.
ADE7858
I2C Write Operation
The write operation using I2C interface of the ADE7858 initiates when the master generates a START condition and consists in one byte representing the address of the ADE7858 followed by the 16-bit address of the target register and by the value of the register. The most significant 7 bits of the address byte constitute the address of the ADE7858 and they are equal to b#0111000. Bit 0 of the address byte is READ/ WRITE bit. Because this is a write operation, it has to be cleared to 0, so the first byte of the write operation is 0x70. After every byte is received, the ADE7858 generates an acknowledge. As registers may have 8, 16 or 32 bits, after the last bit of the register is transmitted and the ADE7858 acknowledges the transfer, the master generates a STOP condition. The addresses and the register content are sent with the most significant bit first. See Figure 60 for details of the I2C write operation.
I2C Read Operation
The read operation using the I2C interface of the ADE7858 is done in two stages. The first stage sets the pointer to the address of the register. The second stage reads the content of the register. As seen in Figure 61, the first stage initiates when the master generates a START condition and consists in one byte representing the address of the ADE7858 followed by the 16-bit address of the target register. The ADE7858 acknowledges every byte received. The address byte is similar to the address byte of a write operation and is equal to 0x70 (See I2C Write Operation section for details). After the last byte of the register address has been sent and it has been acknowledged by the ADE7858, the second stage begins with the master generating a new START condition followed by an address byte. The most significant 7 bits of this address byte constitute the address of the ADE7858 and they are equal to b#0111000. Bit 0 of the address byte is READ/ WRITE bit. Because this is a read operation, it has to be set to 1, so the first byte of the read operation is 0x71. After this byte is received, the ADE7858 generates an acknowledge. Then the ADE7858 sends the value of the register and after every 8 bits are received, the master generates an acknowledge. All the bytes are sent with the most significant bit first. As registers may have 8, 16 or 32 bits, after the last bit of the register is received , the master does not acknowledge the transfer, but does generate a STOP condition.
S T O P S
I2C Compatible Interface
The ADE7858 supports a fully licensed I2C interface. The I2C interface is implemented as a full hardware slave. SDA is the data I/O pin, and SCL is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. The maximum serial clock frequency supported by this interface is 400KHz. The two pins used for data transfer, SDA and SCL are configured in a Wired-AND format that allows arbitration in a multi-master system. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a START condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges, then the data transfer is initiated. This continues until the master issues a STOP condition and the bus becomes idle.
S T A R T S01110000 slave address A C K MS 8 bits of reg address A C K LS 8 bits of reg address A C K Byte3 (MS) of reg
15
8
7
0
31
16
15
8
7
0
7
0
A C K
Byte2 of reg
A C K
Byte1 of reg
A C K
Byte0 (LS) of reg
A C K
ACK generated by ADE7858
Rev. PrA | Page 51 of 76
ADE7858
Figure 60. I2C Write Operation of a 32 bit register
S T A R T S01110000 slave address A C K MS 8 bits of reg address A C K LS 8 bits of reg address A C K
Preliminary Technical Data
15
8
7
0
ACK generated by ADE7858 ACK generated by Master S T A R T S01110001 slave address A C K Byte3 (MS) of reg Byte2 of reg Byte1of reg Byte0 (LS) of reg N O A C 0K
31
A C 16 K 15
A C 8K7
A C 0K7
S T O P S
ACK generated by ADE7858
Figure 61. I2C Read Operation of a 32-bit register
SPI Compatible Interface
The Serial Peripheral Interface (SPI) of the ADE7858 is always a slave of the communication and consists in four pins: SCLK, MOSI, MISO and SS . The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7858 at the MOSI logic input on the falling edge of SCLK and ADE7858 samples it on the rising edge of SCLK. Data is shifted out of the ADE7858 at the MISO logic output on a falling edge of SCLK and can be sampled by the master device on the raising edge of SCLK. The most significant bit of the word is shifted in and out first. The maximum serial clock frequency supported by this interface is 2.5MHz. MISO stays in high impedance when no data is transmitted from the ADE7858. Figure 62 presents details of the connection between ADE7858 SPI and a master device containing an SPI interface. The SS logic input is the chip select input. This input is used when multiple devices share the serial bus. The SS input should be driven low for the entire data transfer operation. Bringing SS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. A new transfer can then be initiated by bringing the SS logic input back low. However, because aborting a data transfer
before completion leaves the accessed register in a state that cannot be guaranteed, every time a register is written, its value should be verified by reading it back.
ADE7858 MOSI MISO SCLK SS\ MOSI MISO SCK SS\
SPI device
Figure 62. Connecting ADE7858 SPI with an SPI device
The protocol is similar to the protocol used in I2C interface.
SPI Read Operation
The read operation using the SPI interface of the ADE7858 initiates when the master sets SS pin low and begins sending one byte representing the address of the ADE7858 on the MOSI line. The master sets data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the
Rev. PrA| Page 52 of 76
Preliminary Technical Data
ADE7858 samples data on the low to high transitions of SCLK. The most significant 7 bits of the address byte can have any value, but as a good programming practice, they should be different from b#0111000, the 7 bits used in the I2C protocol. Bit 0 (READ/ WRITE ) of the address byte must be 1 for a read operation. Next, the master sends the 16-bit address of the register that is read. After the ADE7858 receives the last bit of address of the register on a low-to-high transition of SCLK, it
ADE7858
begins to transmit its content on the MISO line when the next SCLK high-to-low transition occurs, so the master can sample the data on low to high SCLK transition. After the master receives the last bit, it sets SS and SCLK lines high and the communication ends. The data lines MOSI and MISO go in high impedance state. See Figure 63 for details of the SPI read operation.
SS
SCLK
15 14
1
0
MOSI
00000001
Reg Address
31 30 1 0
MISO
Figure 63. SPI read operation of a 32-bit register
Register Value
SS
SCLK
15 14
1
0 31 30
1
0
MOSI
00000000
Reg Address
Register Value
Figure 64. SPI Write operation of a 32-bit register
SPI Write Operation
The write operation using the SPI interface of the ADE7858 initiates when the master sets SS pin low and begins sending one byte representing the address of the ADE7858 on the MOSI line. The master sets data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the ADE7858 samples data on the low to high transitions of SCLK. The most significant 7 bits of the address byte can have any value, but as a good programming practice, they should be
different from b#0111000, the 7 bits used in the I2C protocol. Bit 0 (READ/ WRITE ) of the address byte must be 0 for a write operation. Next, the master sends the 16-bit address of the register that is written and the 32, 16 or 8-bit value of that register without losing any SCLK cycle. After the last bit is transmitted, the master sets SS and SCLK lines high at the end of SCLK cycle and the communication ends. The data lines MOSI and MISO go in high impedance state. See Figure 64 for details of the SPI write operation.
Rev. PrA | Page 53 of 76
ADE7858
HSDC Interface
The High Speed Data Capture (HSDC) interface is disabled after default. It can be used only if the ADE7858 is configured with I2C interface. The SPI interface cannot be used in conjunction with HSDC. Bit 6 (HSDCEN) in CONFIG[15:0] register activates HSDC when set to 1. If bit HSDCEN is cleared to 0, the default value, the HSDC interface is disabled. Setting bit HSDCEN to 1 when SPI is in usage does not have any effect. HSDC is an interface that is used to send to an external device, usually a microprocessor or a DSP, up to fifteen 32-bit words. The words represent the instantaneous values of the phase currents and voltages, active, reactive and apparent powers. The registers being transmitted are: IAWV[23:0], VAWV[23:0], IBWV[23:0], VBWV[23:0], ICWV[23:0], VCWV[23:0], AVA[23:0], BVA[23:0], CVA[23:0], AWATT[23:0], BWATT[23:0], CWATT[23:0], AVAR[23:0], BVAR[23:0] and CVAR[23:0]. All are 24-bit registers that are sign extended to 32-bits (see Figure 18 for details). HSDC can be interfaced with SPI or similar interfaces. HSDC is always a master of the communication and consists in 3 pins: HSA, HSD and HSCLK. HSA represents the select signal. It stays active low or high when a word is transmitted and is usually connected to the select pin of the slave. HSD is used to send data to the slave and is usually connected to the data input pin of the slave. HSCLK is the serial clock line. It is generated by the ADE7858 and is usually connected to the serial clock input of the slave. Figure 65 presents the connections between ADE7858 HSDC and slave devices containing SPI interface. The HSDC communication is managed by the HSDC_CFG[7:0] register (see Table 19). It is recommended to set HSDC_CFG register to the desired value before enabling the port using bit 6 (HSDCEN) in CONFIG[15:0] register. In this way, the state of various pins belonging to HSDC port do not take levels inconsistent with the desired HSDC behaviour. After a hardware reset or after power up, the pins MISO/HSD and
SS /HSA are set high.
Preliminary Technical Data
HCLK is 1, the clock frequency is 4MHz. A bit of data is transmitted for every HSCLK high to low transition. The slave device that receives data from HSDC samples HSD line on the low to high transition of HSCLK.
ADE7858 HSD HSCLK HSA MISO SCK SS
SPI device
Figure 65. Connecting ADE7858 HSDC with an SPI
The words may be transmitted as 32-bit packages or as 8-bit packages. When bit 1 (HSIZE) in HSDC_CFG[7:0] register is 0, the default value, the words are transmitted as 32-bit packages. When bit HSIZE is 1, the registers are transmitted as 8-bit packages. HSDC interface transmits the words with MSB first. Bit 2 (HGAP) introduces a gap of 7 HSCLK cycles between packages when is set to 1. When bit HGAP is cleared to 0, the default value, no gap is introduced between packages and the communication time is shortest. In this case, HSIZE does not have any influence on the communication and a bit is put on HSD line every HSCLK high to low transition. Bits 4,3 (HXFER[1:0]) decide how many words are transmitted. When HXFER[1:0] is 00, the default value, then all fifteen words are transmitted. When HXFER[1:0] is 01, then only the words representing the instantaneous values of phase currents and phase voltages are transmitted in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV and one 32-bit word that is always equal to 0. When HXFER[1:0] is 10, then only the instantaneous values of phase powers are transmitted in the following order: AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR and CVAR. The value 11 for HXFER[1:0] is reserved and writing it is equivalent to writing 00, the default value.
Bit 0 (HCLK) in HSDC_CFG[7:0] register determines the serial clock frequency of the HSDC communication. When HCLK is 0, the default value, then the clock frequency is 8MHz. When
Table 19. HSDC_CFG register
Bit Location 0 1 2 4,3 Bit Mnemonic HCLK HSIZE HGAP HXFER[1:0] Default Value 0 0 0 00
Description -0: HSCLK is 8MHz -1: HSCLK is 4MHz -0: HSDC transmits the 32bit registers in 32bit packages, most significant bit first. -1: HSDC transmits the 32bit registers in 8bit packages, most significant bit first. -0: no gap is introduced between packages. -1: a gap of 7 HCLK cycles is introduced between packages. -00=HSDC transmits 16 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, one 32-bit word always equal to 0 , AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR and CVAR -01= HSDC transmits six instantaneous values of currents and voltages plus one 32-bit word that is always equal to 0 in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,
Rev. PrA| Page 54 of 76
Preliminary Technical Data
Bit Location Bit Mnemonic Default Value
ADE7858
Description VCWV and one 32-bit word always equal to 0 -10= HSDC transmits 9 instantaneous values of phase powers: AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR and CVAR -11=reserved. If set, the ADE7858 behaves as if HXFER[1:0]=00. -0: HSACTIVE output pin is active LOW. -1: HSACTIVE output pin is active HIGH Reserved. These bits do not manage any functionality.
5 7,6
HSAPOL
0 00
Bit 5 (HSAPOL) determines the polarity of HSA pin during the communication. When HSAPOL is 0, the default value, the HSA pin is active low during the communication. This means that HSA stays high when no communication is in progress. When the communication starts, HSA goes low and stays low until the communication ends. Then it goes back high. When HSAPOL is 1, the HSA pin is active high during the communication. This means that HSA stays low when no communication is in progress. When the communication starts, HSA goes high and stays high until the communication ends. Then it goes back low. Bits 7,6 of HSDC_CFG are reserved. Any value written into these bits does not have any consequence on HSDC behavior. Figure 66 shows the HSDC transfer protocol for HGAP=0, HXFER[1:0]=00 and HSAPOL=0. Note that the HSDC interface sets a bit on HSD line every HSCLK high to low transition and the value of bit HSIZE is irrelevant. Figure 67 shows the HSDC transfer protocol for HSIZE=0, HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC interface introduces a 7 HSCLK cycles gap between every 32-bit word. Figure 68 shows the HSDC transfer protocol for HSIZE=1, HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC interface introduces a 7 HSCLK cycles gap between every 8-bit word. Table 20 presents the time it takes to execute an HSDC data transfer for all HSDC_CFG[7:0] settings. For some settings, the
transfer time is less than 125usec (8KHz), the waveform sample registers update rate. This means the HSDC port transmits data every sampling cycle. For settings in which the transfer time is greater than 125usec, the HSDC port transmits data only in the first of two consecutive 8KHz sampling cycles. This means it transmits registers at an effective rate of 4KHz.
Table 20. Communication times for various HSDC settings
HXFER[1:0] 00 00 00 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 HGAP 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 HSIZE * * 0 0 1 1 * * 0 0 1 1 * * 0 0 1 1 HCLK 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comm Time [sec] 64 128 77.125 154.25 119.25 238.25 28 56 33.25 66.5 51.625 103.25 36 72 43 86 66.625 133.25
HSCLK
31 HSD
0
31
0
31
0
31
0
IAVW (32bit)
VAWV(32bit)
IBWV(32bit)
CVAR(32bit)
HSA
Figure 66. HSDC communication for HGAP=0, HXFER[1:0]=00 and HSAPOL=0. HSIZE is irrelevant
Rev. PrA | Page 55 of 76
ADE7858
SCLK
Preliminary Technical Data
31 HSDATA
0
31
0
31
0
31
0
IAVW (32bit) 7 HCLK cycles
VAWV(32bit) 7 HCLK cycles
IBWV(32bit)
CVAR (32bit)
HSACTIVE
Figure 67. HSDC communication for HSIZE=0, HGAP=1, HXFER[1:0]=00 and HSAPOL=0
SCLK
31 HSDATA
24
23
16
15
8
7
0
IAVW (Byte 3) 7 HCLK cycles
IAWV (Byte 2) 7 HCLK cycles
IAWV(Byte 1)
CVAR(Byte 0)
HSACTIVE
Figure 68. HSDC communication for HSIZE=1, HGAP=1, HXFER[1:0]=00 and HSAPOL=0
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Preliminary Technical Data REGISTERS LIST
Table 21. ADE7858 Registers List located in DSP data memory RAM
Bit Length 24 24 24 24 24 24 N/A 24 24 24 24 24 24 N/A 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 N/A 24 24 24 Bit Length during Comm2 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE N/A 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE N/A 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE 32 ZPSE N/A 32 ZP 32 ZP 32 ZP Default Value 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000
ADE7858
Address 0x4380 0x4381 0x4382 0x4383 0x4384 0x4385 0x4386 0x4387 0x4388 0x4389 0x438A 0x438B 0x438C 0x438D 0x438E 0x438F 0x4390 0x4391 0x4392 0x4393 0x4394 0x4395 0x4396 0x4397 0x4398 0x4399 0x439A 0x439B 0x439C 0x439D0x43A8 0x43A9 0x43AA 0x43AB
Name AIGAIN AVGAIN BIGAIN BVGAIN CIGAIN CVGAIN Reserved AIRMSOS AVRMSOS BIRMSOS BVRMSOS CIRMSOS CVRMSOS Reserved AVAGAIN BVAGAIN CVAGAIN AWGAIN AWATTOS BWGAIN BWATTOS CWGAIN CWATTOS AVARGAIN AVAROS BVARGAIN BVAROS CVARGAIN CVAROS Reserved VATHR1 VATHR0 WTHR1
R/W1 R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W
Type3 S S S S S S N/A S S S S S S N/A S S S S S S S S S S S S S S S N/A U U U
0x43AC
WTHR0
R/W
24
32 ZP
U
0x000000
0x43AD
VARTHR1
R/W
24
32 ZP
U
0x000000
0x43AE
VARTHR0
R/W
24
32 ZP
U
0x000000
0x43AF
reserved
N/A
N/A
N/A
N/A
0x000000
Description Phase A current gain adjust Phase A voltage gain adjust Phase B current gain adjust Phase B voltage gain adjust Phase C current gain adjust Phase C voltage gain adjust For proper operation, this memory location should be kept at 0x000000. Phase A current rms offset Phase A voltage rms offset Phase B current rms offset Phase B voltage rms offset Phase C current rms offset Phase C voltage rms offset For proper operation, this memory location should be kept at 0x000000. Phase A apparent power gain adjust Phase B apparent power gain adjust Phase C apparent power gain adjust Phase A total active power gain adjust Phase A total active power offset adjust Phase B total active power gain adjust Phase B total active power offset adjust Phase C total active power gain adjust Phase C total active power offset adjust Phase A total reactive power gain adjust Phase A total reactive power offset adjust Phase B total reactive power gain adjust Phase B total reactive power offset adjust Phase C total reactive power gain adjust Phase C total reactive power offset adjust These memory locations should be kept at 0x000000 for proper operation Most significant 24 bits of VATHR[47:0] threshold used in phase apparent power data path. Less significant 24 bits of VATHR[47:0] threshold used in phase apparent power data path. Most significant 24 bits of WTHR[47:0] threshold used in phase total/fundamental active power data path. Less significant 24 bits of WTHR[47:0] threshold used in phase total/fundamental active power data path. Most significant 24 bits of VARTHR[47:0] threshold used in phase total/fundamental reactive power data path. Less significant 24 bits of VARTHR[47:0] threshold used in phase total/fundamental reactive power data path. This memory location should be kept at 0x000000 for proper operation
Rev. PrA | Page 57 of 76
ADE7858
Address 0x43B0 0x43B1 0x43B2 0x43B30x43B4 0x43B5 Name VANOLOAD APNOLOAD VARNOLOAD reserved DICOEFF R/W 24 32 ZPSE S R/W1 R/W R/W R/W Bit Length 24 24 24 Bit Length during Comm2 32 ZPSE 32 ZPSE 32 ZPSE Type3 S S S Default Value 0x0000000 0x0000000 0x0000000 0x000000 0x0000000
Preliminary Technical Data
Description No-load threshold in the apparent power data path No-load threshold in the total/fundamental active power data path No-load threshold in the total/fundamental reactive power data path These locations should not be written for proper operation Register used in the digital integrator algorithm. If the integrator is turned on, it must be set at 0xFF8000 Disables/enables the HPF in the current data path (see Table 25) These memory locations should be kept at 0x000000 for proper operation Phase A current rms value Phase A voltage rms value Phase B current rms value Phase B voltage rms value Phase C current rms value Phase C voltage rms value These memory locations should not be written for proper operation
0x43B6 0x43B70x43BF 0x43C0 0x43C1 0x43C2 0x43C3 0x43C4 0x43C5 0x43C60x43FF
1
HPFDIS reserved AIRMS AVRMS BIRMS BVRMS CIRMS CVRMS reserved
R/W
24
32 ZP
U
0x000000 0x000000
R R R R R R
24 24 24 24 24 24
32 ZP 32 ZP 32 ZP 32 ZP 32 ZP 32 ZP
S S S S S S
NA NA NA NA NA NA 0x000000
R=read W=write 32 ZPSE=24-bit signed register that is transmitted as a 32-bit word with 4 most significant bits padded with 0s and sign extended to 28bits 32 ZP=28 or 24-bit signed or unsigned register that is transmitted as a 32-bit word with 4 or respectively 8 most significant bits padded with 0s 3 U=unsigned register S=signed register in two's complement format
2
Rev. PrA| Page 58 of 76
Preliminary Technical Data
Table 22. Internal DSP memory RAM registers
Address 0xE203 0xE228
1
ADE7858
Default Value 0x0000 0x0000
Name reserved RUN
R/W1 R/W R/W
Bit Length 16 16
Bit Length during Comm 16 16
Type2 U U
Description This memory location should not be written for proper operation. RUN register starts and stops the DSP. See Digital Signal Processor chapter for more details.
R=read W=write 2 U=unsigned register S=signed register in two's complement format
Rev. PrA | Page 59 of 76
ADE7858
Table 23. ADE7858 billable registers
Address 0xE400 0xE401 0xE402 0xE4030xE405 0xE406 0xE407 0xE408 0xE4090xE40B 0xE40C 0xE40D 0xE40E
1
Preliminary Technical Data
Bit Length 32 32 32 N/A 32 32 32 N/A 32 32 32 Bit Length during Comm 32 32 32 N/A 32 32 32 N/A 32 32 32 Default Value 0x00000000 0x00000000 0x00000000 Can have any value 0x00000000 0x00000000 0x00000000 Can have any value 0x00000000 0x00000000 0x00000000
Name AWATTHR BWATTHR CWATTHR Reserved AVARHR BVARHR CVARHR Reserved AVAHR BVAHR CVAHR
R/W1 R R R N/A R R R N/A R R R
Type2 S S S N/A S S S N/A S S S
Description Phase A total active energy accumulation Phase B total active energy accumulation Phase C total active energy accumulation Reserved Phase A total reactive energy accumulation Phase B total reactive energy accumulation Phase C total reactive energy accumulation Reserved Phase A apparent energy accumulation Phase B apparent energy accumulation Phase C apparent energy accumulation
2
R=read W=write U=unsigned register S=signed register in two's complement format
Rev. PrA| Page 60 of 76
Preliminary Technical Data
Table 24. Configuration and power quality registers
Bit Length 32 32 32 32 N/A 24 24 24 32 32 24 24 24 N/A 24 24 24 24 24 24 24 24 24 24 24 24 32 24 Bit Length during comm2 32 32 32 32 N/A 32 ZP 32 ZP 32 ZP 32 32 32 SE 32 SE 32 SE N/A 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 SE 32 32 ZP Default Value NA NA NA NA N/A 0xFFFFFF 0xFFFFFF 0x000000 0x00000000 0x00000000 NA NA NA N/A NA NA NA NA NA NA NA NA NA NA NA NA 0x93D774E6 0x000000
ADE7858
Address 0xE500 0xE501 0xE502 0xE503 0xE5040xE506 0xE507 0xE508 0xE509 0xE50A 0xE50B 0xE50C 0xE50D 0xE50E 0xE50F 0xE510 0xE511 0xE512 0xE513 0xE514 0xE515 0xE516 0xE517 0xE518 0xE519 0xE51A 0xE51B 0xE51F 0xE520 0xE5210xE52E 0xE600 0xE601 0xE602 0xE603 0xE6040xE606 0xE607 0xE608 0xE6090xE60B 0xE60C 0xE60D 0xE60E 0xE60F
Name IPEAK VPEAK STATUS0 STATUS1 Reserved OILVL OVLVL SAGLVL MASK0 MASK1 IAWV IBWV ICWV Reserved VAWV VBWV VCWV AWATT BWATT CWATT AVAR BVAR CVAR AVA BVA CVA CHECKSUM VNOM reserved PHSTATUS ANGLE0 ANGLE1 ANGLE2 reserved PERIOD PHNOLOAD reserved LINECYC ZXTOUT COMPMODE GAIN
R/W1 R R R R N/A R/W R/W R/W R/W R/W R R R N/A R R R R R R R R R R R R R R/W
Type3 U U U U N/A U U U U U S S S N/A S S S S S S S S S S S S U S
Description Current peak register. See Figure 31 and Table 26 for details about its composition. Voltage peak register. See Figure 31 and Table 27 for details about its composition. Interrupt status register 0. (See Table 28) Interrupt status register 1. (See Table 29) Reserved Overcurrent threshold Overvoltage threshold Voltage sag level threshold Interrupt enable register 0. (See Table 30) Interrupt enable register 1. (See Table 31) Instantaneous value of phase A current Instantaneous value of phase B current Instantaneous value of phase C current Reserved Instantaneous value of phase A voltage Instantaneous value of phase B voltage Instantaneous value of phase C voltage Instantaneous value of phase A total active power Instantaneous value of phase B total active power Instantaneous value of phase B total active power Instantaneous value of phase A total reactive power Instantaneous value of phase B total reactive power Instantaneous value of phase B total reactive power Instantaneous value of phase A apparent power Instantaneous value of phase Bapparent power Instantaneous value of phase B apparent power Checksum verification. See Checksum Register section for details Nominal phase voltage rms used in the alternative computation of the apparent power These addresses should not be written for proper operation Phase peak register. (See Table 32) Time delay 0. See Time Interval Between Phases section for details Time delay 1. See Time Interval Between Phases section for details Time delay 2. See Time Interval Between Phases section for details These addresses should not be written for proper operation Network line period Phase no-load register. (See Table 33) These addresses should not be written for proper operation Line cycle accumulation mode count Zero crossing timeout count Computation mode register. (See Table 34) PGA gains at ADC inputs. (See Table 35)
R R R R
16 16 16 16
16 16 16 16
U U U U
NA NA NA NA
R R
16 16
16 16
U U
NA NA
R/W R/W R/W R/W
16 16 16 16
16 16 16 16
U U U U
0xFFFF 0xFFFF 0x01FF 0x0000
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ADE7858
Address 0xE610 0xE611 0xE612 0xE613 0xE614 0xE615 0xE616 0xE617 0xE618 0xE700 0xE701 0xE702 0xE703 0xE704 0xE705 Name CFMODE CF1DEN CF2DEN CF3DEN APHCAL BPHCAL CPHCAL PHSIGN CONFIG MMODE ACCMODE LCYCMODE PEAKCYC SAGCYC CFCYC R/W1 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Bit Length 16 16 16 16 10 10 10 16 16 8 8 8 8 8 8 Bit Length during comm2 16 16 16 16 16 ZP 16 ZP 16 ZP 16 16 8 8 8 8 8 8 Type3 U U U U U U U U U U U U U U U Default Value 0x0E88 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 NA 0x0000 0x16 0x00 0x78 0x00 0x00 0x01
Preliminary Technical Data
Description CFx, x=1,2,3 configuration register. (See Table 36) CF1 denominator CF2 denominator CF3 denominator Phase calibration of phase A. (See Table 37) Phase calibration of phase B. (See Table 37) Phase calibration of phase C. (See Table 37) Power sign register. (See Table 38) ADE7858 configuration register. (See Table 39) Measurement mode register. (See Table 40) Accumulation mode register. (SeeTable 41) Line accumulation mode behavior. (See Table 42) Peak detection half line cycles Sag detection half line cycles Number of CF pulses between two consecutive energy latches. See Synchronizing energy registers with CFx outputs section HSDC configuration register. (See Table 43) Version of die This address may be used in manipulating the SS pin when SPI is chosen as the active port. (See Serial Interfaces chapter for details) For proper operation, do not write to this address. Configuration register used during PSM1 mode. (See Table 44)
0xE706 0xE707 0xEBFF
HSDC_CFG VERSION reserved
R/W R/W
8 8 8
8 8 8
U U
0x00 -
0xEC00 0xEC01
1
Reserved CONFIG2
N/A R/W
N/A 8
N/A 8
N/A U
N/A 0x00
R=read W=write 2 32 ZP=24 or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or respectively 12 most significant bits padded with 0s 32 SE=24-bit signed register that is transmitted as a 32-bit word sign extended to 32 bits 16 ZP=10-bit unsigned register that is transmitted as a 16-bit word with 6 most significant bits padded with 0s 3 U=unsigned register S=signed register in two's complement format
Rev. PrA| Page 62 of 76
Preliminary Technical Data
Table 25. HPFDIS register (address 0x43B6)
Bit Location 23:0 Bit Mnemonic Default value 00000000 Description
ADE7858
When HPFDIS=0x00000000, then all high pass filters in voltage and current channels are enabled. When the register is set to any non zero value, all high pass filters are disabled.
Table 26. IPEAK register (address 0xE500)
Bit Location 23-0 24 25 26 31-27 Bit Mnemonic IPEAKVAL[23:0] IPPHASE[0] IPPHASE[1] IPPHASE[2] Default value 0 0 0 0 00000 Description These bits contain the peak value determined in the current channel. When this bit is set to 1, phase A current generated IPEAKVAL[23:0] value. When this bit is set to 1, phase B current generated IPEAKVAL[23:0] value. When this bit is set to 1, phase C current generated IPEAKVAL[23:0] value. These bits are always 0.
Table 27. VPEAK register (address 0xE501)
Bit Location 23-0 24 25 26 31-27 Bit Mnemonic VPEAKVAL[23:0] VPPHASE[0] VPPHASE[1] VPPHASE[2] Default value 0 0 0 0 00000 Description These bits contain the peak value determined in the voltage channel. When this bit is set to 1, phase A voltage generated VPEAKVAL[23:0] value. When this bit is set to 1, phase B voltage generated VPEAKVAL[23:0] value. When this bit is set to 1, phase C voltage generated VPEAKVAL[23:0] value. These bits are always 0.
Table 28. STATUS0 register (address 0xE502)
Bit Location 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bit Mnemonic AEHF Reserved REHF Reserved VAEHF LENERGY REVAPA REVAPB REVAPC REVPSUM1 REVRPA REVRPB REVRPC REVPSUM2 CF1 Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description When this bit is set to 1, it indicates that bit 30 of any one of the total active energy registers AWATTHR, BWATTHR, CWATTHR has changed. This bit is always set to 0. When this bit is set to 1, it indicates that bit 30 of any one of the total reactive energy registers AVARHR, BVARHR, CVARHR has changed. This bit is always set to 0. When this bit is set to 1, it indicates that bit 30 of any one of the apparent energy registers AVAHR, BVAHR, CVAHR has changed. When this bit is set to 1, in line energy accumulation mode, it indicates the end of an integration over an integer number of half line cycles set in LINECYC[15:0] register. When this bit is set to 1, it indicates that the phase A total active power has changed sign. The sign itself is indicated in bit 0 (AWSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the phase B total active power has changed sign. The sign itself is indicated in bit 1 (BWSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the phase C total active power has changed sign. The sign itself is indicated in bit 2 (CWSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data path has changed sign. The sign itself is indicated in bit 3 (SUM1SIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the phase A total reactive power has changed sign. The sign itself is indicated in bit 4 (AVARSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the phase B total reactive power has changed sign. The sign itself is indicated in bit 5 (BVARSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the phase C total reactive power has changed sign. The sign itself is indicated in bit 6 (CVARSIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data path has changed sign. The sign itself is indicated in bit 7 (SUM2SIGN) of PHSIGN[15:0] register (see Table 38). When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin, that is an active low pulse has been generated. The bit is set even if the CF1 output is disabled by setting bit 9 (CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is determined by bits 2-0 (CF1SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it indicates a high to low transition has occurred at CF2 pin, that is an active
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15
CF2
ADE7858
Bit Location Bit Mnemonic Default value
Preliminary Technical Data
Description low pulse has been generated. The bit is set even if the CF2 output is disabled by setting bit 10 (CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is determined by bits 5-3 (CF2SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it indicates a high to low transition has occurred at CF3 pin, that is an active low pulse has been generated. The bit is set even if the CF3 output is disabled by setting bit 11 (CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is determined by bits 8-6 (CF3SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it indicates that all periodical (at 8KHz rate) DSP computations have finished. When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 data path has changed sign. The sign itself is indicated in bit 8 (SUM3SIGN) of PHSIGN[15:0] register (see Table 38). Reserved. These bits are always 0.
16
CF3
17 18 31-19
DREADY REVPSUM3 Reserved
0 0 0 0000 0000 0000
Table 29. STATUS1 register (address 0xE503)
Bit Location 0 Bit Mnemonic NLOAD Default value 0 Description When this bit is set to 1, it indicates that at least one phase entered no-load condition based on total active and reactive powers. The phase is indicated in bits 2-0 (NLPHASE) in PHNOLOAD[15:0] register (see Table 33). This bit is always set to 0. When this bit is set to 1, it indicates that at least one phase entered no-load condition based on apparent power. The phase is indicated in bits 8-6 (VANLPHASE) in PHNOLOAD[15:0] register (see Table 33). When this bit is set to 1, it indicates a zero crossing on phase A voltage is missing. When this bit is set to 1, it indicates a zero crossing on phase B voltage is missing. When this bit is set to 1, it indicates a zero crossing on phase C voltage is missing. When this bit is set to 1, it indicates a zero crossing on phase A current is missing. When this bit is set to 1, it indicates a zero crossing on phase B current is missing. When this bit is set to 1, it indicates a zero crossing on phase C current is missing. When this bit is set to 1, it indicates a zero crossing has been detected on phase A voltage. When this bit is set to 1, it indicates a zero crossing has been detected on phase B voltage. When this bit is set to 1, it indicates a zero crossing has been detected on phase C voltage. When this bit is set to 1, it indicates a zero crossing has been detected on phase A current. When this bit is set to 1, it indicates a zero crossing has been detected on phase B current. When this bit is set to 1, it indicates a zero crossing has been detected on phase C current. In case of a software reset command, bit 7 (SWRST) set to 1 in CONFIG[15:0] register, or a transition from PSM1, PSM2 or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the end of the transition process and after all registers changed value to default. IRQ1 pin goes low to signal this moment because this interrupt cannot be disabled. When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated by bits 14-12 (VSPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases indicated by bits 5-3 (OIPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases indicated by bits 11-9 (OVPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it indicates a negative to positive zero crossing on phase A voltage was not followed by a negative to positive zero crossing on phase B voltage, but by a negative to positive zero crossing on phase C voltage. Reserved. This bit is always set to 0. Reserved. This bit is always set to 1. Reserved. This bit is always set to 0. When this bit is set to 1, it indicates that the period used to detect the peak value in the current channel has ended. IPEAK[31:0] register contains the peak value and the phase where the peak has been detected (see Table 26).
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1 2
Reserved VANLOAD
0 0
3 4 5 6 7 8 9 10 11 12 13 14 15
ZXTOVA ZXTOVB ZXTOVC ZXTOIA ZXTOIB ZXTOIC ZXVA ZXVB ZXVC ZXIA ZXIB ZXIC RSTDONE
0 0 0 0 0 0 0 0 0 0 0 0 1
16 17 18 19
SAG OI OV SEQERR
0 0 0 0
20 21 22 23
Reserved Reserved Reserved PKI
0 1 0 0
Preliminary Technical Data
Bit Location 24 Bit Mnemonic PKV Default value 0
ADE7858
31:25
Reserved
000 0000
Description When this bit is set to 1, it indicates that the period used to detect the peak value in the voltage channel has ended. VPEAK[31:0] register contains the peak value and the phase where the peak has been detected (see Table 27). Reserved. These bits are always 0.
Table 30. MASK0 register (address 0xE50A)
Bit Location 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bit Mnemonic AEHF Reserved REHF Reserved VAEHF LENERGY REVAPA REVAPB REVAPC REVPSUM1 REVRPA REVRPB REVRPC REVPSUM2 CF1 Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description When this bit is set to 1, it enables an interrupt when bit 30 of any one of the total active energy registers AWATTHR, BWATTHR, CWATTHR changes. This bit does not manage any functionality. When this bit is set to 1, it enables an interrupt when bit 30 of any one of the total reactive energy registers AVARHR, BVARHR, CVARHR changes. This bit does not manage any functionality. When this bit is set to 1, it enables an interrupt when bit 30 of any one of the apparent energy registers AVAHR, BVAHR, CVAHR changes. When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of an integration over an integer number of half line cycles set in LINECYC[15:0] register. When this bit is set to 1, it enables an interrupt when the phase A total active power changes sign. When this bit is set to 1, it enables an interrupt when the phase B total active power changes sign. When this bit is set to 1, it enables an interrupt when the phase C total active power changes sign. When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1 data path changes sign. When this bit is set to 1, it enables an interrupt when the phase A total reactive power changes sign. When this bit is set to 1, it enables an interrupt when the phase B total reactive power changes sign. When this bit is set to 1, it enables an interrupt when the phase C total reactive power changes sign. When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2 data path changes sign. When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF1 pin, that is an active low pulse is generated. The interrupt may be enabled even if the CF1 output is disabled by setting bit 9 (CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is determined by bits 2-0 (CF1SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF2 pin, that is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is disabled by setting bit 10 (CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is determined by bits 5-3 (CF2SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin, that is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is disabled by setting bit 11 (CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is determined by bits 8-6 (CF3SEL) in CFMODE[15:0] register (see Table 36). When this bit is set to 1, it enables an interrupt when all periodical (at 8KHz rate) DSP computations finish. When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3 data path changes sign. Reserved. These bits do not manage any functionality.
15
CF2
16
CF3
17 18 31-19
DREADY REVPSUM3 Reserved
0 0 00 0000 0000 0000
Table 31. MASK1 register (address 0xE50B)
Bit Location 0 Bit Mnemonic NLOAD Default value 0 Description When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition based on total active and reactive powers.
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ADE7858
Bit Location 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bit Mnemonic Reserved VANLOAD ZXTOVA ZXTOVB ZXTOVC ZXTOIA ZXTOIB ZXTOIC ZXVA ZXVB ZXVC ZXIA ZXIB ZXIC RSTDONE SAG OI OV SEQERR Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description This bit does not manage any functionality. When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition based on apparent power. When this bit is set to 1, it enables an interrupt when a zero crossing on phase A voltage misses. When this bit is set to 1, it enables an interrupt when a zero crossing on phase B voltage misses. When this bit is set to 1, it enables an interrupt when a zero crossing on phase C voltage misses. When this bit is set to 1, it enables an interrupt when a zero crossing on phase A current misses. When this bit is set to 1, it enables an interrupt when a zero crossing on phase B current is missing. When this bit is set to 1, it enables an interrupt when a zero crossing on phase C current is missing. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A voltage. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B voltage. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C voltage. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A current. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B current. When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C current. Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality attached. It can be set to 1 or cleared to 0 without having any effect. When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the phases indicated by bits 14-12 (VSPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the phases indicated by bits 5-3 (OIPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of the phases indicated by bits 11-9 (OVPHASE) in PHSTATUS[15:0] register (see Table 32). When this bit is set to 1, it enables an interrupt when a negative to positive zero crossing on phase A voltage is not followed by a negative to positive zero crossing on phase B voltage, but by a negative to positive zero crossing on phase C voltage. Reserved. These bits do not manage any functionality. When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in the current channel has ended. When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in the voltage channel has ended. Reserved. These bits do not manage any functionality.
20,22,21 23 24 31:25
Reserved PKI PKV Reserved
00 0 0 000 0000
Table 32. PHSTATUS register (address 0xE600)
Bit Location 2-0 3 4 5 8-6 9 10 11 12 13 14 15 Bit Mnemonic Reserved OIPHASE[0] OIPHASE[1] OIPHASE[2] Reserved OVPHASE[0] OVPHASE[1] OVPHASE[2] VSPHASE[0] VSPHASE[1] VSPHASE[2] Reserved Default value 000 0 0 0 000 0 0 0 0 0 0 0 Description Reserved . These bits are always 0. When this bit is set to 1, phase A current generated bit 17 (OI) in STATUS1[31:0] When this bit is set to 1, phase B current generated bit 17 (OI) in STATUS1[31:0] When this bit is set to 1, phase C current generated bit 17 (OI) in STATUS1[31:0] Reserved. These bits are always 0. When this bit is set to 1, phase A voltage generated bit 18 (OV) in STATUS1[31:0] When this bit is set to 1, phase B voltage generated bit 18 (OV) in STATUS1[31:0] When this bit is set to 1, phase C voltage generated bit 18 (OV) in STATUS1[31:0] When this bit is set to 1, phase A voltage generated bit 16 (SAG) in STATUS1[31:0] When this bit is set to 1, phase B voltage generated 16 (SAG) in STATUS1[31:0] When this bit is set to 1, phase C voltage generated 16 (SAG) in STATUS1[31:0] Reserved . This bit is always 0.
Table 33. PHNOLOAD register (address 0xE608)
Bit Location 0 Bit Mnemonic NLPHASE[0] Default value 0 Description -0: phase A is out of no-load condition based on total active/reactive powers. -1: phase A is in no load condition based on total active/reactive powers. Bit set together with
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Preliminary Technical Data
Bit Location 1 Bit Mnemonic NLPHASE[1] Default value 0
ADE7858
Description bit 0 (NLOAD) in STATUS1[31:0]. -0: phase B is out of no-load condition based on total active/reactive powers. -1: phase B is in no load condition based on total active/reactive powers. Bit set together with bit 0 (NLOAD) in STATUS1[31:0]. -0: phase C is out of no-load condition based on total active/reactive powers. -1: phase C is in no load condition based on total active/reactive powers. Bit set together with bit 0 (NLOAD) in STATUS1[31:0]. Reserved. These bits are always 0. -0: phase A is out of no-load condition based on apparent power. -1: phase A is in no load condition based on apparent power. Bit set together with bit 2 (VANLOAD) in STATUS1[31:0]. -0: phase B is out of no-load condition based on apparent power. -1: phase B is in no load condition based on apparent power. Bit set together with bit 2 (VANLOAD) in STATUS1[31:0]. -0: phase C is out of no-load condition based on apparent power. -1: phase C is in no load condition based on apparent power. Bit set together with bit 2 (VANLOAD) in STATUS1[31:0]. Reserved . These bits are always 0.
2
NLPHASE[2]
0
3-5 6
Reserved VANLPHASE[0]
000 0
7
VANLPHASE[1]
0
8
VANLPHASE[2]
0
15-9
Reserved
000 0000
Table 34. COMPMODE register (address 0xE60E)
Bit Location 0 1 2 3 4 5 6 7 8 10,9 Bit Mnemonic TERMSEL1[0] TERMSEL1[1] TERMSEL1[2] TERMSEL2[0] TERMSEL2[1] TERMSEL2[2] TERMSEL3[0] TERMSEL3[1] TERMSEL3[2] ANGLESEL[1:0] Default value 1 1 1 1 1 1 1 1 1 00 Description Setting all TERMSEL1[2:0] to 1 signifies the sum of all 3 phases is included in CF1 output Phase A is included in CF1 outputs calculations Phase B is included in CF1 outputs calculations Phase C is included in CF1 outputs calculations Setting all TERMSEL2[2:0] to 1 signifies the sum of all 3 phases is included in CF2 output Phase A is included in CF2 outputs calculations Phase B is included in CF2 outputs calculations Phase C is included in CF2 outputs calculations Setting all TERMSEL3[2:0] to 1 signifies the sum of all 3 phases is included in CF3 output Phase A is included in CF3 outputs calculations Phase B is included in CF3 outputs calculations Phase C is included in CF3 outputs calculations -00:the angles between phase voltages and phase currents are measured -01: the angles between phase voltages are measured -10: the angles between phase currents are measured -11: no angles are measured When this bit is 0, the apparent power on phase A is computed regularly. When this bit is 1, the apparent power on phase A is computed using VNOM[23:0] register instead of regular measured rms phase voltage. When this bit is 0, the apparent power on phase B is computed regularly. When this bit is 1, the apparent power on phase B is computed using VNOM[23:0] register instead of regular measured rms phase voltage. When this bit is 0, the apparent power on phase C is computed regularly. When this bit is 1, the apparent power on phase C is computed using VNOM[23:0] register instead of regular measured rms phase voltage. Reserved. These bits do not manage any functionality.
11
VNOMAEN
0
12
VNOMBEN
0
13
VNOMCEN
0
14,15
Reserved
00
Table 35: GAIN register (address 0xE60F)
Bit 2 to 0 Mnemonic PGA1[2:0] Default 000 Description Phase currents gain selection -000: gain=1 -001: gain=2
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ADE7858
Preliminary Technical Data
-010: gain=4 -011: gain=8 -100: gain=16 -101, 110, 111: reserved. When set, the ADE7858 behaves like PGA1 [2:0]=000 Reserved. These bits do not manage any functionality. Phase voltages gain selection -000: gain=1 -001: gain=2 -010: gain=4 -011: gain=8 -100: gain=16 -101, 110, 111: reserved. When set, the ADE7858 behaves like PGA3 [2:0]=000 Reserved. These bits do not manage any functionality.
5 to 3 8 to 6
Reserved PGA3[2:0]
000 000
15 to 9
Reserved
000 0000
Table 36. CFMODE register (address 0xE610)
Bit Location 2-0 Bit Mnemonic CF1SEL[2:0] Default value 000 Description -000: CF1 frequency proportional to the sum of total active powers on each phase identified by bits 2-0 (TERMSEL1) in COMPMODE[15:0] register. -001: CF1 frequency proportional to the sum of total reactive powers on each phase identified by bits 2-0 (TERMSEL1) in COMPMODE[15:0] register. -010: CF1 frequency proportional to the sum of apparent powers on each phase identified by bits 2-0 (TERMSEL1) in COMPMODE[15:0] register. -011,100, 101,110,111: reserved. When set, the ADE7858 behaves like CF1SEL [2:0]=000. -000: CF2 frequency proportional to the sum of total active powers on each phase identified by bits 5:3 (TERMSEL2) in COMPMODE[15:0] register. -001: CF2 frequency proportional to the sum of total reactive powers on each phase identified by bits 5:3 (TERMSEL2) in COMPMODE[15:0] register. -010: CF2 frequency proportional to the sum of apparent powers on each phase identified by bits 5:3 (TERMSEL2) in COMPMODE[15:0] register. -011,100,101,110,111: reserved. When set, the ADE7858 behaves like CF2SEL [2:0]=000. -000: CF3 frequency proportional to the sum of total active powers on each phase identified by bits 8:6 (TERMSEL3) in COMPMODE[15:0] register. -001: CF3 frequency proportional to the sum of total reactive powers on each phase identified by bits 8:6 (TERMSEL3) in COMPMODE[15:0] register. -010: CF3 frequency proportional to the sum of apparent powers on each phase identified by bits 8:6 (TERMSEL3) in COMPMODE[15:0] register. -011,100,101,110,111: reserved. When set, the ADE7858 behaves like CF3SEL [2:0]=000. When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency converter remains enabled even if CF1DIS=1. When set to 0, the CF1 output is enabled. When this bit is set to 1, the CF2 output is disabled. The respective digital to frequency converter remains enabled even if CF2DIS=1. When set to 0, the CF2 output is enabled. When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency converter remains enabled even if CF3DIS=1. When set to 0, the CF3 output is enabled. When this bit is set to 1, the content of the corresponding energy registers is latched when a CF1 pulse is generated. See Synchronizing energy registers with CFx outputs section. When this bit is set to 1, the content of the corresponding energy registers is latched when a CF2 pulse is generated. See Synchronizing energy registers with CFx outputs section. When this bit is set to 1, the content of the corresponding energy registers is latched when a CF3 pulse is generated. See Synchronizing energy registers with CFx outputs section. Reserved. This bit does not manage any functionality.
5-3
CF2SEL[2:0]
001
8-6
CF3SEL[2:0]
010
9 10 11 12 13 14 15
CF1DIS CF2DIS CF3DIS CF1LATCH CF2LATCH CF3LATCH Reserved
1 1 1 0 0 0 0
Table 37. APHCAL, BPHCAL, CPHCAL registers (addresses 0xE614, 0xE615, 0xE616)
Bit Location 9-0 Bit Mnemonic PHCALVAL Default value 0000000000 Description If current channel compensation is necessary, these bits can vary only between 0 and 383.
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Preliminary Technical Data
Bit Location Bit Mnemonic Default value Description
ADE7858
15-10
Reserved
000000
If voltage channel compensation is necessary, these bits can vary only between 512 and 575. If PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves like PHCALVAL set between 256 and 383. If PHCALVAL bits are set with numbers between 512 and 1023, the compensation behaves like PHCALVAL bits set between 384 and 511. Reserved. These bits do not manage any functionality.
Table 38. PHSIGN register (address 0xE617)
Bit Location 0 1 2 3 Bit Mnemonic AWSIGN BWSIGN CWSIGN SUM1SIGN Default value 0 0 0 0 Description -0: if the total active power on phase A is positive. -1: if the total active power on phase A is negative. -0: if the total active power on phase B is positive. -1: if the total active power on phase B is negative. -0: if the total active power on phase C is positive. -1: if the total active power on phase is negative. -0: if the sum of all phase powers in the CF1 data path is positive. -1: if the sum of all phase powers in the CF1 data path is negative. Phase powers in the CF1 data path are identified by bits 2,1,0 (TERMSEL1) of COMPMODE[15:0] register and by bits 2,1,0 (CF1SEL) of CFMODE[15:0] register. -0: if the reactive power identified by bit 7 (REVRPSEL) bit in ACCMODE[7:0] register (total of fundamental) on phase A is positive. -1: if the total reactive power on phase A is negative. -0: if the total reactive power on phase B is positive. -1: if the total reactive power on phase B is negative. -0: if the total reactive power on phase C is positive. -1: if the total reactive power on phase C is negative. -0: if the sum of all phase powers in the CF2 data path is positive. -1: if the sum of all phase powers in the CF2 data path is negative. Phase powers in the CF2 data path are identified by bits 5,4,3 (TERMSEL2) of COMPMODE[15:0] register and by bits 5,4,3 (CF2SEL) of CFMODE[15:0] register. -0: if the sum of all phase powers in the CF3 data path is positive. -1: if the sum of all phase powers in the CF3 data path is negative. Phase powers in the CF3 data path are identified by bits 8,7,6 (TERMSEL3) of COMPMODE[15:0] register and by bits 8,7,6 (CF3SEL) of CFMODE[15:0] register. Reserved . These bits are always 0.
4
AVARSIGN
0
5 6 7
BVARSIGN CVARSIGN SUM2SIGN
0 0 0
8
SUM3SIGN
0
15-9
Reserved
000 0000
Table 39. CONFIG register (address 0xE618)
Bit Location 0 Bit Mnemonic INTEN Default value 0 Description Integrator Enable. When this bit is set to 1, the internal digital integrator is enabled for use in meters utilizing Rogowski Coils on all 3 phase and neutral current inputs. When this bit is cleared to 0, the internal digital integrator is disabled. Reserved. These bits do not manage any functionality. When this bit is set to 1, the voltage channel outputs are swapped with the current channel outputs. Thus, the current channel information will be present in the voltage channel registers and vice versa. When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put to ground. When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put to ground. When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at CF3/HSCLK pin. When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
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2,1 3
Reserved SWAP
00 0
4 5 6
MOD1SHORT MOD2SHORT HSDCEN
0 0 0
ADE7858
Bit Location 7 9,8 Bit Mnemonic SWRST VTOIA[1:0] Default value 0 00 Description
Preliminary Technical Data
11,10
VTOIB[1:0]
00
13,12
VTOIC[1:0]
00
14 15
Reserved Reserved
0 0
When this bit is set to 1, a software reset is initiated. These bits decide what phase voltage is considered together with phase A current in the power path: 00=phase A voltage 01=phase B voltage 10=phase C voltage 11=reserved. When set, the ADE7858 behaves like VTOIA [1:0]=00 These bits decide what phase voltage is considered together with phase B current in the power path: 00=phase B voltage 01=phase C voltage 10=phase A voltage 11=reserved. When set, the ADE7858 behaves like VTOIB [1:0]=00 These bits decide what phase voltage is considered together with phase C current in the power path: 00=phase C voltage 01=phase A voltage 10=phase B voltage 11=reserved. When set, the ADE7858 behaves like VTOIC [1:0]=00 Reserved. This bit does not manage any functionality. Reserved. This bit does not manage any functionality.
Table 40. MMODE register (address 0xE700)
Bit Location 1,0 Bit Mnemonic PERSEL[1:0] Default value 00 Description -00: Phase A selected as source of the voltage line period measurement -01: Phase B selected as source of the voltage line period measurement -10: Phase C selected as source of the voltage line period measurement -11:Reserved. When set, the ADE7858 behaves like PERSEL[1:0]=00 PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all 3 phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak measurement period indicated in PEAKCYC[7:0] register decreases accordingly because zero crossings are detected on more than one phase. When this bit is set to 1, phase A is selected for the voltage and current peak registers When this bit is set to 1, phase B is selected for the voltage and current peak registers When this bit is set to 1, phase C is selected for the voltage and current peak registers Reserved. These bits do not manage any functionality.
2
PEAKSEL[0]
1
3 4 7-5
PEAKSEL[1] PEAKSEL[2] Reserved
1 1 000
Table 41. ACCMODE Register (Address 0xE701)
Bit Location 1,0 Bit Mnemonic WATTACC[1:0] Default value 00 Description -00: signed accumulation mode of the total active powers -01: reserved. When set, the ADE7858 behaves like WATTACC[1:0]=00 -10: reserved. When set, the ADE7858 behaves like WATTACC[1:0]=00 -11: absolute accumulation mode of the total active powers -00: signed accumulation of the total reactive powers -01: reserved. When set, the ADE7858 behaves like VARACC[1:0]=00 -10:the total reactive power are accumulated depending on the sign of the total active power: -if the active power is positive, the reactive power is accumulated as is -if the active power is negative, the reactive power is accumulated with reversed sign -11: reserved. When set, the ADE7858 behaves like VARACC[1:0]=00 These bits are used to select the inputs to the energy accumulation registers. IA', IB' and IC' are IA, IB and IC shifted respectively by -90. -00: 3 phase 4 wires with 3 voltage sensors
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3,2
VARACC[1:0]
00
5,4
CONSEL[1:0]
00
Preliminary Technical Data
Bit Location Bit Mnemonic Default value Description -01: 3 phase 3 wires delta connection -10: 3 phase 4 wires with 2 voltage sensors -11: 3 phase 4 wires delta connection Energy CONSEL[1:0]=00 CONSEL[1:0]=01 Registers VA x IA VA x IA AWATTHR, AFWATTHR VB x IB 0 BWATTHR, BFWATTHR VC x IC VC x IC CWATTHR, CFWATTHR VA x IA' VA x IA' AVARHR, AFVARHR VB x IB' 0 BVARHR, BFVARHR VC x IC' VC x IC' CVARHR, CFVARHR AVAHR VARMS x IARMS VARMS x IARMS BVAHR VBRMS x IBRMS 0 CVAHR VCRMS x ICRMS VCRMS x ICRMS Reserved. These bits do not manage any functionality.
ADE7858
CONSEL[1:0]=10 VA x IA VB=-VA-VC VB x IB VC x IC VA x IA' VB=-VA-VC VB x IB' VC x IC' VARMS x IARMS VBRMS x IBRMS VCRMS x ICRMS
CONSEL[1:0]=11 VA x IA VB=-VA VB x IB VC x IC VA x IA' VB=-VA VB x IB' VC x IC' VARMS x IARMS VBRMS x IBRMS VCRMS x ICRMS
7,6
Reserved
00
Table 42. LCYCMODE register (address 0xE702)
Bit Location 0 Bit Mnemonic LWATT Default value 0 Description -0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR) are placed in regular accumulation mode. -1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR) are placed into linecycle accumulation mode. -0: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed in regular accumulation mode. -1: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed into line-cycle accumulation mode. -0: the va-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed in regular accumulation mode. -1: the va-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed into line-cycle accumulation mode. -0: phase A is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase A is selected for zero crossings counts in the line cycle accumulation mode. If more than one phase is selected for zero crossing detection, the accumulation time is shorten accordingly -0: phase B is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase B is selected for zero crossings counts in the line cycle accumulation mode. -0: phase C is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase C is selected for zero crossings counts in the line cycle accumulation mode. -0: Read-with-reset of all energy registers is disabled. This bit should be cleared to 0 when bits 2,1,0 (LWATT, LVAR, LVA) are set to 1. -1: Read-with-reset of all xWATTHR, xVARHR, xVAHR registers (x=A,B,C) is enabled. This means a read of those registers resets them to 0. Reserved. This bit does not manage any functionality.
1
LVAR
0
2
LVA
0
3
ZXSEL[0]
1
4 5 6
ZXSEL[1] ZXSEL[2] RSTREAD
1 1 1
7
Reserved
0
Table 43. HSDC_CFG register (address 0xE706)
Bit Location 0 1 Bit Mnemonic HCLK HSIZE Default value 0 0 Description -0: HSCLK is 8MHz -1: HSCLK is 4MHz -0: HSDC transmits the 32bit registers in 32bit packages, most significant bit first.
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ADE7858
Bit Location 2 4,3 Bit Mnemonic HGAP HXFER[1:0] Default value 0 00
Preliminary Technical Data
Description -1: HSDC transmits the 32bit registers in 8bit packages, most significant bit first. -0: no gap is introduced between packages. -1: a gap of 7 HCLK cycles is introduced between packages. -00=HSDC transmits 16 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, one 32-bit word equal to 0, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR and CVAR -01= HSDC transmits six instantaneous values of currents and voltages plus one 32-bit word that is always equal to 0 in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV and one 32-bit word equal to 0. -10= HSDC transmits 9 instantaneous values of phase powers: AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR and CVAR -11=reserved. If set, the ADE7858 behaves as if HXFER[1:0]=00. -0: HSACTIVE output pin is active LOW. -1: HSACTIVE output pin is active HIGH Reserved. These bits do not manage any functionality.
5 7,6
HSAPOL Reserved
0 00
Table 44. CONFIG2 register (address 0xEC01)
Bit Location 0 1 Bit Mnemonic EXTREFEN I2C_LOCK Default value 0 0 Description When this bit is 0, signifies the internal voltage reference is used in the ADCs. When this bit is 1, an external reference is connected to the pin 17 REF in/out When this bit is 0, the SS /HSA pin can be toggled 3 times to activate the SPI port. If I2C is the active serial port, this bit must be set to 1 to lock it in. From this moment on, spurious togglings of the SS pin and an eventual switch into using SPI port is no longer possible. If SPI is the active serial port, any write to CONFIG2[7:0] register locks the port. From this moment on, a switch into using I2C port is no longer possible. Once locked, the serial port choice is maintained when the ADE7858 changes PSMx, x=0,1,2,3 power modes. Reserved. These bits do not manage any functionality.
7-2
Reserved
0
Rev. PrA| Page 72 of 76
Preliminary Technical Data OUTLINE DIMENSIONS
ADE7858
Figure 69. 40-Lead Lead Frame Chip Scale package [LFCSP_WQ], 6 x 6 mm Body, Very Very Thin Quad (CP-40-10) Dimensions shown in millimeters
ORDERING GUIDE
Model ADE7858ACPZ ADE7858ACPZ-RL EVAL-ADE7858EBZ ADE7858ACPZ-REF Temperature Range -40C to +85C -40C to +85C Package Description 40-Lead LFCSP 40-Lead LFCSP, Reel ADE7858 evaluation board ADE7858 Reference Design Package Option CP-40-1 CP-40-1
Rev. PrA| Page 73 of 76
ADE7858 NOTES
Preliminary Technical Data
Rev. PrA| Page 74 of 76
Preliminary Technical Data NOTES
ADE7858
Rev. PrA| Page 75 of 76
ADE7858 NOTES
Preliminary Technical Data
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08510-0-11/09(PrA)
Rev. PrA| Page 76 of 76

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